EM78159NAS EMC [ELAN Microelectronics Corp], EM78159NAS Datasheet - Page 19

• Manufacturer Part Number: EM78159NAS
• Description: 8-Bit Microcontroller with OTP ROM
• Manufacturer: EMC [ELAN Microelectronics Corp]

1
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
4.3 TCC/WDT & Prescaler
4.2.9 IOCF (Interrupt Mask Register)
Bit 0 (TCIE): TCIF interrupt enable bit
Bit 1 (ICIE): ICIF interrupt enable bit
Bit 2 (EXIE): EXIF interrupt enable bit
Bits 3~7:
Individual interrupt is enabled by setting its associated control bit in the IOCF to "1."
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
Refer to Figure 4-7 in Section 4.6 for further reference.
IOCF register is both readable and writable.
There are two 8-bit counters available as prescalers for the TCC and WDT
respectively. The PSR0 ~ PSR2 bits of the CONT register are used to determine the
ratio of the prescaler of TCC, and the PWR0 ~ PWR2 bits of the IOCE register are used
to determine the prescaler of WDT. The prescaler (PSR0 ~ PSR2) will be cleared by
the instruction each time it writes to TCC. The WDT and prescaler will be cleared by
the “WDTC” and “SLEP” instructions.
Bit 7
-
external clock input (edge selectable from TCC pin). If TCC signal is sourced
from internal clock, TCC will increase by 1 at every instruction cycle (without
prescaler). CLK=Fosc/2 or CLK=Fosc/4 application is determined by the CODE
Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0," and CLK=Fosc/4 is
used if CLK bit is "1." If TCC signal source comes from external clock input, TCC
is increased by 1 at every falling edge or rising edge of TCC pin.
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in Sleep mode).
During normal operation or Sleep mode, a WDT time-out (if enabled) will cause
the device to reset. The WDT can be enabled or disabled any time during Normal
mode by software programming. Refer to WDTE bit of IOCE register in Section
4.2.8. Without prescaler, the WDT time-out period is approximately 18 ms
(default).
Bit 6
Not used
0 = disable TCIF interrupt
1 = enable TCIF interrupt
0 = disable ICIF interrupt
1 = enable ICIF interrupt
0 = disable EXIF interrupt
1 = enable EXIF interrupt
-
Bit 5
-
Bit 4
-
Bit 3
-
8-Bit Microcontroller with OTP ROM
EXIE
Bit 2
Bit 1
ICIE
EM78P159N
TCIE
Bit 0
1
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