HT46R94 HOLTEK [Holtek Semiconductor Inc], HT46R94 Datasheet
HT46R94
Related parts for HT46R94
HT46R94 Summary of contents
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... As is the case with all Holtek microcontroller devices, the HT46R94 is fully supported by a full suite of professional hardware and software tools, containing comprehensive features to ensure user applications are designed and debugged in as short a time as possible. ...
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... Block Diagram Pin Assignment Rev. 1.10 2 HT46R94 November 5, 2008 ...
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... VSSD, PD & PE port negative power supply, ground VSSE Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function the table applies to the larger package size not all pins may exist on the smaller packages. Rev. 1.10 Description 3 HT46R94 November 5, 2008 ...
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... No load, system HALT load, system HALT load, system HALT 5V No load, 3V system HALT 0 0. 0.9V DD 1.98 2.98 3.98 V =0. =0. HT46R94 Ta=25 C Typ. Max. Unit 5.5 V 5.5 5 100 ...
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... =0. =0. =0. =2.7V~5.5V 1.6 AVDD V =5V, 2 AVDD REF AVDD HT46R94 Typ. Max. Unit 1 0 100 2.5 2 REF V + AVDD V 0.1 2 LSB 4 LSB 0.5 1 ...
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... With prescaler (f /4096 131 With prescaler (f /4096 Wake-up from HALT 0.25 1 0.5 6 HT46R94 Ta=25 C Typ. Max. Unit 4000 kHz 8000 kHz 32768 kHz 4000 kHz 8000 kHz 90 180 s 65 130 s 369 737 ms 266 532 ms 125 ms s ...
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... JMP or CALL that demand a jump to a non-consecutive Program Memory address. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly address- able by user. System Clocking and Pipelining Instruction Fetching 7 HT46R94 /4 with a 1:3 high/low duty cycle. November 5, 2008 ...
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... Program Counter + # S10 Program Counter 8 HT46R94 ...
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... Program Memory will be transferred to the user de- fined Data Memory register [m] as specified in the in- struction. The higher order table data byte from the Program Memory will be transferred to the TBLH special 9 HT46R94 November 5, 2008 ...
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... TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed. Table Location Bits PC8 @ Table Location 10 HT46R94 November 5, 2008 ...
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... By using the SET [m].i and CLR [m].i instructions individual bits can be set or reset un- der program control giving the user a large range of flex- ibility for bit manipulation in the Data Memory. Special Purpose Data Memory 11 HT46R94 November 5, 2008 ...
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... Memory Pointer that the microcontroller will be directed to. ; setup size of block ; setup memory pointer with first RAM address ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared 12 HT46R94 November 5, 2008 ...
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... OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction cleared by a system power-up or executing the CLR WDT or HALT instruction set by a WDT time-out. Status Register 13 HT46R94 November 5, 2008 ...
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... PA and PB. There are also outputs on ports PC, PD and PE. These I/O ports are mapped to the Data Memory with specific addresses as shown in the Special Purpose Data Memory table. For input oper- ation, these ports are non-latching, which means the in- 14 HT46R94 November 5, 2008 ...
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... Converter Control Register, ADCR, must be properly set. There are no configuration options associated with the A/D function. If used as I/O pins, then full pull-high resistor configuration options remain, how- ever if used as A/D inputs then any pull-high resistor options associated with these pins will be automati- cally disconnected. 15 HT46R94 timer November 5, 2008 ...
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... Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, PA Input/Output Ports PB Input/Output Ports 16 HT46R94 November 5, 2008 ...
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... Rev. 1.10 PC0~PC3 Output Ports PC4~PC7 Output Ports PD0 Input/Output Port PD1~PD7, PE Output Ports 17 HT46R94 November 5, 2008 ...
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... Use software to generate the VDD, VSS, VDD/2 volt- ) while OL2 ages by changing COM pins PC4~7 to output high, ). The D.C. OH3 output low and input respectively. Generate the segment timing using other I/O ports with outputs equal to either VSS or VDD. LCD Control Register 18 HT46R94 1/2 Bias On/Off Off Off ...
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... However, if the counter is en- abled and counting, any new data written into the preload register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. 19 HT46R94 November 5, 2008 ...
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... Timer/Event Counter 0 Control Register Timer/Event Counter 1 Control Register Rev. 1.10 20 HT46R94 November 5, 2008 ...
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... When it is full and overflows, an interrupt signal is generated and Bit7 Bit6 the Timer/Event Counter will reload the value already loaded into the preload register and continue counting The interrupt can be disabled by ensuring that the asso- 21 HT46R94 Bit7 Bit6 0 1 November 5, 2008 ...
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... The PFD output is pin-shared with the I/O pin PA7. The PFD function is selected via configuration option, how- ever, if not selected, the pin can operate as a normal I/O pin. The timer overflow signal from Timer/Event Counter 1 is the clock source for the PFD circuit. The output fre- 22 HT46R94 November 5, 2008 ...
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... Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. PFD Output Control 23 HT46R94 November 5, 2008 ...
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... Name four individual modulation sub-sections, known as the PWM0 7+1 mode or the 6+2 mode respectively. The device can PWM1 choose which mode to use by selecting the appropriate PWM2 configuration option. Note that it is only necessary to 24 HT46R94 November 5, 2008 ...
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... The first group which consists of bit1~bit7 is de- noted here as the DC value. The second group which consists of bit0 is known as the AC value. In the 7+1 PWM mode, the duty cycle value of each of the two mod- ulation sub-cycles is shown in the following table. 6+2 PWM Mode 25 HT46R94 DC AC (0~3) (Duty Cycle) DC+1 i<AC 64 ...
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... PWM Programming Example value)/256 The following sample program shows how the PWM outputs are setup and controlled. Before use the corre- sponding PWM output configuration options must first be selected. PA4 will remain low 7+1 PWM Mode 26 HT46R94 November 5, 2008 ...
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... AN0~AN7 will all be set as analog in- puts. Note that if the PCR2~PCR0 bits are all set to zero, then all the Port B pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power consumption. A/D Converter Structure 27 HT46R94 Bit Bit Bit Bit Bit Bit ...
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... A/D Converter Clock Source Register - ACSR The clock source for the A/D converter, which originates from the system clock f ratio, the value of which is determined by the ADCS1 and ADCS0 bits in the ACSR register. 28 HT46R94 ADONB Bit A/D Circuits X Off ...
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... START bit in the ADCR register must first be set high and then im- mediately cleared to zero. This will ensure that the EOCB flag is correctly set to a high condition. 29 HT46R94 ADCS2, ADCS1, ADCS0=011 Undefined Undefined Undefined ...
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... This ability to re- duce power by turning off the internal A/D function by clearing the A/D channel selection bits may be an impor- tant consideration in battery powered applications. The A/D can also be turned off by using the ADONB bit int he ACSR register. 30 HT46R94 AD November 5, 2008 ...
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... A/D inputs ; and select AN0 to be connected to the A the Port B channel bits have changed the ; following START signal(0-1-0) must be issued ; within 10 instruction cycles ; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt 31 HT46R94 /8 as SYS November 5, 2008 ...
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... LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the V Ideal A/D Transfer Function 32 HT46R94 level. DD November 5, 2008 ...
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... WDT clock source configuration option must also select the 32768Hz oscillator as its clock source, otherwise unpredictable system operation may occur. HALT Instruction MODS RC/XTAL Oscillator Not Executed 0 Not Executed 1 Executed x Operation Mode 33 HT46R94 32768Hz On On Off On Off On November 5, 2008 ...
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... By controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding re- quest flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Control 0 Registers Interrupt Control 1 Registers 34 HT46R94 November 5, 2008 ...
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... LCDEN bit in the LCDC register to zero and the PD0 bit set high. If the external interrupt enable bit is not set then the pin can be used as a PD0 CMOS output pin. When the interrupt is enabled, the stack is not full and a high to 35 HT46R94 Vector Priority 04H 1 ...
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... Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. Time Base Interrupt 36 HT46R94 November 5, 2008 ...
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... RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initi- ated from this point. RES Reset Timing Chart 37 HT46R94 November 5, 2008 ...
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... To ensure reliable continuation of normal program execution after a reset occurs important to know what condition the microcontroller is in after a particular reset occurs. The accompanying table describes how each type of reset affects each of the microcontroller internal registers. 38 HT46R94 November 5, 2008 ...
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... HT46R94 WDT Time-out (HALT ...
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... The external capacitor shown on the diagram does not influence the frequency of os- cillation. Rf 470k External RC Oscillator 40 HT46R94 TBD TBD TBD TBD TBD ...
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... Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. Rf TBD 41 HT46R94 TBD TBD TBD November 5, 2008 ...
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... If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended. 42 HT46R94 November 5, 2008 ...
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... PAC0 and PAC1 of the PAC port control register to zero. The PA0 data bit in the PA data register must also be set high to enable the buzzer outputs, if set low, Watchdog Timer 43 HT46R94 , ...
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... Buzzer Output Pin Control 44 HT46R94 Output Function PA0=BZ PA1=BZ PA0= 0 PA1= 0 ...
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... LVR function: enable or disable 15 LVR voltage: 2.1V, 3.15V or 4.2V Lock Options 16 Lock All 17 Partial Lock Rev. 1.10 Options / SYS SP /4, f / HT46R94 SYS November 5, 2008 ...
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... Application Circuits Rev. 1.10 46 HT46R94 November 5, 2008 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 47 HT46R94 November 5, 2008 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 48 HT46R94 Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 Description 49 HT46R94 Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.10 50 HT46R94 November 5, 2008 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.10 addr 51 HT46R94 November 5, 2008 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT46R94 November 5, 2008 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.10 addr 53 HT46R94 November 5, 2008 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.10 Stack Stack Stack [m]. 0~6) 54 HT46R94 November 5, 2008 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.10 [m]. 0~6) 55 HT46R94 November 5, 2008 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.10 [ HT46R94 November 5, 2008 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.10 0 [m] [ HT46R94 November 5, 2008 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.10 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 58 HT46R94 November 5, 2008 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.10 59 HT46R94 November 5, 2008 ...
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... Package Information 44-pin QFP (10mm´10mm) Outline Dimensions Symbol Rev. 1.10 Dimensions in mm Min. Nom. 13 9.9 13 9.9 0.8 0.3 1.9 0.25 0.73 0.1 0 HT46R94 Max. 13.4 10.1 13.4 10.1 2.2 2.7 0.5 0.93 0.2 7 November 5, 2008 ...
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... QFP (14mm´14mm) Outline Dimensions Symbol Rev. 1.10 Dimensions in mm Min. Nom. 17.3 13.9 17.3 13.9 1 0.4 2.5 0.1 0.73 0 HT46R94 Max. 17.5 14.1 17.5 14.1 3.1 3.4 1.03 0.2 7 November 5, 2008 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 62 HT46R94 November 5, 2008 ...