HY5DU281622ETP-25 HYNIX [Hynix Semiconductor], HY5DU281622ETP-25 Datasheet - Page 16

• Manufacturer Part Number: HY5DU281622ETP-25
• Description: 128M(8Mx16) gDDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 1.0 / Oct. 2005
7.
8.
9.
Power-Up Sequence
Note)
1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device
2. The Power Voltage ramp time between initial VDD and VDDmin must be no less than 3ms.
3. The Initial VDD must be maintained under 100mV.
latch-up. VDDQ, VTT and VREF must be equal to or less than VDD+0.3V. Alternatively, VTT may be 1.35V
maximum during power up, even if VDD/VDDQ are 0V. Once initialized, including self refresh mode, VREF must
always be powered within specified range.
VDD
VDDQ
VTT
VREF
/CLK
CLK
CKE
CMD
DM
ADDR
A10
BA0, BA1
DQS
DQ'S
Issue Precharge commands for all banks of the device.
Issue 2 or more Auto Refresh commands.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
LVCMOS Low Level
tVTD
VDD and CK stable
Power UP
T=200usec
tIS tIH
NOP
Precharge All
PRE
tRP
EMRS Set
CODE
CODE
CODE
EMRS
tMRD
(with A8=H)
Reset DLL
MRS Set
CODE
CODE
CODE
MRS
tMRD
NOP
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
Precharge All
PRE
tRP
Auto Refresh
2 or more
AREF
tXSRD*
tRFC
(with A8=L)
MRS Set
CODE
CODE
CODE
MRS
1HY5DU281622ETP
tMRD
Non-Read
Command
CODE
CODE
CODE
ACT
CODE
CODE
CODE
READ
RD
16