NJ8821BADP GEC [General Electric Company], NJ8821BADP Datasheet - Page 3

• Manufacturer Part Number: NJ8821BADP
• Description: FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE) WITH RESETTABLE COUNTERS
• Manufacturer: GEC [General Electric Company]

PIN DESCRIPTIONS
9,10, 11, 12
15, 16, 17
Pin no.
7, 8
13
14
18
19
20
1
2
3
4
5
6
2·0
1·5
1·0
0·5
Fig. 3 Typical supply current v. input frequency
V
OSC IN, F
DD
OSC OUT
1
DS0-DS2
OSC IN/
= 5V
D0-D3
Name
PDA
PDB
V
V
MC
NC
CH
LD
F
PE
RB
DD
2
SS
IN
IN
= 0V TO 5V SQUARE WAVE
3
INPUT FREQUENCY (MHz)
Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Output at
(V
decreases as f
by gain (programmed by RB).
Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
The input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when
a full logic swing is available, may be DC-coupled.
Negative supply (ground).
Positive supply.
These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. An external reference signal may, alternatively, be
applied to OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may
be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being
twice the programmed number.
Data on these inputs is transferred to the internal data latches during the appropriate data read time
slot. D3 is MSB, D0 is LSB.
No connection
This pin is used as a strobe for the data. A logic ‘1’ on this pin transfers data from the D0-D3 pins to
the internal latch addressed by the data select (DS0-DS2) pins . A logic ‘0’ disables the data inputs.
Data select inputs for addressing the internal data latches
Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning
of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and
remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset.
This gives a total division ratio of MP 1 A , where P and P 11 represent the dual-modulus prescaler
values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a
division ratio up to and including 4128/129. The programming range of the ‘M’ counter is 8-1023
and, for correct operation, M > A . Where every possible channel is required, the minimum total division
ratio should be P
An external sample and hold phase comparator gain programming resistor should be connected
between this pin and V
An external hold capacitor should be connected between this pin and V
DD
4
TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO F
AND OSC IN
2V
f
f
f
v
v
v
5
SS
. f
= f
, f
)/2 when the system is in lock. Voltage increases as f
OSC IN
r
r
r
6
or f
or f
and phase error within PDA window: high impedance.
r
phase lead increases. Output is linear over only a narrow phase window, determined
v
r
2
7
2 P .
leading: negative pulses with respect to the bias point V
leading: positive pulses with respect to the bias point V
F
IN
8
SS
.
IN
9
10
Description
Fig. 4 Typical supply current v. input level, OSC IN
8
7
6
5
4
3
2
1
0·2
0·4
INPUT LEVEL (V RMS)
V
0V TO 5V SQUARE WAVE
1MHz
F
DD
IN
0·6
v
= LOW FREQUENCY
= 5V
phase lead increases; voltage
0·8
SS
.
BIAS
10MHz
BIAS
1·0
1·2
1·4
NJ8821
1·6
3