NJ8821BADP GEC [General Electric Company], NJ8821BADP Datasheet - Page 4

• Manufacturer Part Number: NJ8821BADP
• Description: FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE) WITH RESETTABLE COUNTERS
• Manufacturer: GEC [General Electric Company]

NJ8821
PROGRAMMING
microprocessor, and allows the user to change the data in
selected latches as defined by the data map Fig.5. The PE pin
is used as a strobe for the data: taking PE high causes data to
be transferred from the data pins (D0-D3) into the addressed
latch. Following the falling edge of PE, the data is retained in
the addressed latch and the data inputs are disabled. Data
transfer from all internal latches into the counters occurs
simultaneously with the transfer of data into latch 1, which
would therefore normally be the last latch addressed during
each channel change. Timing information for this mode of
operation is given in Fig. 6.
reloading with the new counter values. This means that the
synthesiser loop lock-up time is well defined and less than
PHASE COMPARATORS
output, PDB, which provides a ‘coarse’ error signal to enable
fast switching between channels. The PDB output is active
until the phase error is within the sample and hold phase
detector, PDA, window, when PDB becomes high impedance.
Phase-lock is indicated at this point by a low level on LD. The
sample and hold phase detector provides a ‘fine’ error signal
to give further phase adjustment and to hold the loop in lock.
output from both the reference and main divider chains, is
sampled at the reference frequency to give the ‘fine’ error
signal, PDA. When in phase lock, this output would be typically
at (V
to phase error. The relationship between this offset and the
4
Timing is generated externally, normally from a
When re-programming, a reset to zero state is followed by
The digital phase/frequency detector drives a three-state
An internally generated ramp, controlled by the digital
DD
2V
SS
)/2 and any offset from this would be proportional
DS0-DS2
D0 - D3
PE
t
SE
t
DS
Fig. 6 Timing diagram
t
W(ST)
only small changes in frequency, the GPS NJ8823 (with non-
resettable counters) should be considered.
phase error is the phase comparator gain, which is
programmable with an external resistor, RB. An internal 50pF
capacitor is used in the sample and hold comparator.
enhanced at high frequencies by the inclusion of a resistor
between pin 8 (OSC OUT) and the other components. A value
of 150-270 is advised.
PROGRAMMING/POWER UP
them prior to the application of V
occur.
CRYSTAL OSCILLATOR
10ms. If shorter lock-up times are are required when making
WORD
t
DH
When using the internal oscillator, the stability may be
Data and signal input pins should not have input applied to
1
2
3
4
5
6
7
8
t
HE
DS2
0
0
0
0
1
1
1
1
DS1
0
0
1
1
0
0
1
1
Fig. 5 Data map
DS0
0
1
0
1
0
1
0
1
DD
M1
M5
M9
D3
A3
R3
R7
, as otherwise latch-up may
-
-
R10
M0
M4
M8
D2
R2
R6
A2
A6
M3
M7
D1
A1
A5
R1
R5
R9
-
M2
M6
D0
A0
A4
R0
R4
R8
-