AX88140AP ETC, AX88140AP Datasheet - Page 14

• Manufacturer Part Number: AX88140AP
• Description: Fast Ethernet MAC Controller
• Manufacturer: ETC

2.3 Boot ROM , Serial ROM , General-purpose signals group
BR_A<0>
BR_A<1>
BR_AD<7>
BR_AD<6>
BR_AD<5>
BR_AD<4>
BR_AD<3>
BR_AD<2>
BR_AD<1>
BR_AD<0>
BR_CE#
SR_CK
SR_CS
SR_DI
SR_DO
GENP<7>
GENP<6>
GENP<5>
GENP<4>
GENP<3>
GENP<2>
GENP<1>
GENP<0>
2.4 MII/SYM/SRL interface signals group
MCOL
MCRS
MRXDV
MRXERR
MDC
MDIO
MII/SRL
SIGNAL
SIGNAL
AX88140A
TYPE
I/O
I/O
O
O
O
O
0
0
I
Tab - 2 Boot ROM , Serial ROM , General-purpose signals group
FOR 160 PIN
NUMBER
TYPE PIN
I/O
O
O
I
I
I
I
PIN
110,
109,
106,
105,
104,
103,
102,
112
113
101
111
99,
98,
97,
96,
93,
92,
91,
88
89
87
86
90
NUMBER
FOR 160 PIN
126
127
125
124
116
115
147
FOR 144 PIN
NUMBER
100,
PIN
102
103
101
99,
96,
95,
94,
93,
92,
89,
88,
87,
86,
83,
82,
81,
91
78
79
77
76
80
FOR 144 PIN
NUMBER
PIN
Boot ROM address line bit 0.
Boot ROM address line bit 1. This pin also latches the boot ROM
address and control lines by the two external latches.
Boot ROM address and data multiplexed lines bits 7 through 0. In
the first of two consecutive address cycles, these lines contain the
boot ROM address bits 9 through 2; followed by boot ROM
address bits 17 through 10 in the second cycle. During the data
cycle, bits 7 through 0 contain data.
Boot ROM chip enable.
Serial ROM clock signal.
Serial ROM chip-select signal.
Serial ROM data-in signal.
Serial ROM data-out signal.
General-purpose pins can be used by software as either status pins
or control pins. These pins can be configured by software to
perform either input or output functions.
112
113
111
110
106
105
133
14
Collision detected is asserted when detected by an
external physical layer protocol(PHY) device.
Carrier sense is asserted by the PHY when the media
is active.
Data valid is asserted by an external PHY when
receive data is present on the MRXD/SYRXD lines
and is deasserted at the end of the packet. This signal
should be synchronized with the
MRCLK/SYMRCLK signal.
Receive error asserts when a data decoding error is
detected by an external PHY device. This signal is
synchronized to MRCLK/SYMRCLK and can be
asserted for a minimum of one receive clock. When
asserted during a packet reception, it sets the cyclic
redundancy check(CRC) error bit in the receive
descriptor (RDESO).
MII management data clock is sourced by the
AX88140A to the PHY devices as a timing reference
for the transfer of information on the MII_MDIO
signal.
MII management data input/output transfers control
information and status between the PHY and the
AX88140A.
Indicates the selected port: SRL or MII/SYM. When
asserted, the MII/SYM port is active. When
deasserted, the SRL port is active.
DESCRIPTION
ASIX ELECTRONICS CORPORATION
DESCRIPTION
PRELIMINARY