CXP86608 SONY [Sony Corporation], CXP86608 Datasheet
CXP86608
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CXP86608 Summary of contents
Page 1
... CPU, ROM, RAM, I/O ports. The CXP86608/86612/86616 also provide a sleep function that enables to lower the power consumption. Features • A wide instruction set (213 instructions) which covers various types of data — ...
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... CXP86608/86612/86616 ...
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... EXLC pin (input) for the piggyback/evaluator and OTP devices – 3 – CXP86608/86612/86616 64 PC4 63 PC5 62 PC6 61 PC7 60 PF0/PWM0 59 PF1/PWM1 58 PF2/PWM2 57 PF3/PWM3 56 PF4/SCL0 55 PF5/SCL1 54 PF6/SDA0 53 PF7/SDA1 52 PE0/TO/ADJ 51 PE1 50 PE2/TEX/INT0 49 PE3/TX 48 ...
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... Vss (Pins 10 and 42) are both connected to GND. 3. Pin 39 is the NC pin. However, connect EXLC pin (input) for the piggyback/evaluator and OTP devices – 4 – CXP86608/86612/86616 PF3/PWM3 50 PF4/SCL0 49 PF5/SCL1 48 PF6/SDA0 47 PF7/SDA1 46 ...
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... Bits 2 and 3 are clock oscillation. When input port. used as an event Bits 4, 5 and 6 counter, input to TEX pin are output port. and leave TX pin open. (7 pins) – 5 – CXP86608/86612/86616 32kHz oscillation frequency dividing output. External interruption request input. Active at the falling edge ...
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... Connects a crystal for system clock oscillation. When a clock is supplied externally, input to EXTAL pin and input a reversed phase clock to XTAL pin. System reset; active at Low level. No connected. Connect this pin to V Positive power supply. GND. Connect two Vss pins to GND. – 6 – CXP86608/86612/86616 under normal operation. DD ...
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... RD (Port A) Ports data Ports direction "0" after reset RD (Ports INT1 Port C data Data bus RD (Port C) – 7 – CXP86608/86612/86616 IP Input protection circuit Schmitt input IP Schmitt input only for PG7 IP 12V drive Large current 12mA ...
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... Port D direction "0" after reset Schmitt input RD (Port D) SCK, SO Schmitt input only for PD1 RD (Port D) Port D data Port D direction "0" after reset Schmitt input RD (Port D) – 8 – CXP86608/86612/86616 After reset Hi-Z IP Large current 12mA Hi-Z IP Large current 12mA Hi-Z IP Large current 12mA ...
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... ADJ2K provides usage as buzzer output. 2 Pull-up transistor approx. 150k Port E data "1" after reset Port E direction "1" after reset RD (Port – 9 – CXP86608/86612/86616 2 High level (with the resistor of pull-up transistor ON when reset) IP High level IP 32kHz oscillation circuit control " ...
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... Port F data "1" after reset Data bus RD (Port F) SCL, SDA Schmitt input SCL, SDA circuit) Large current 12mA – 10 – CXP86608/86612/86616 After reset Hi-Z 12V drive Large current 12mA Hi-Z BUS internal I C pins (SCL1 for SCL0) Hi-Z ...
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... Circuit format IP • Diagram shows the circuit composition during oscillation. • Feedback resistor is removed during stop. (This device does not enter the stop mode.) Pull-up resistor Mask option OP Schmitt input – 11 – CXP86608/86612/86616 After reset Oscillation Low level (when reset) ...
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... V DD EXTAL pin –0.3 0.4 V –20 +75 °C – 12 – CXP86608/86612/86616 (Vss = 0V reference) Remarks Total of all output pins Ports excluding large current output (value per pin) Large current output ports (value per pin Total of all output pins SDIP-64P-01 QFP-64P-L01 (Vss = 0V reference) Remarks 4 5 ...
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... Sleep mode 5.5V, 16MHz DD crystal oscillation ( 3.3V, 32MHz DD crystal oscillation ( Stop mode V = 5.5V, termination DD of 16MHz and 32MHz oscillation – 13 – CXP86608/86612/86616 (Ta = –20 to +75°C, Vss = 0V reference) Min. Typ. = –0.5mA 4 –1.2mA 3 1.8mA OL = 3.6mA OL = 12.0mA OL = 3.0mA OL = 4.0mA OL = 5.5V 0 0.4V –0 ...
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... For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current when non-resistor is selected. 2 When all output pins are left open. 3 This device does not enter the stop mode. Pins Conditions Clock 1MHz 0V for no measured pins – 14 – CXP86608/86612/86616 Min. Typ. Max. Unit ...
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... XH CF Fig. 1. Clock timing External clock XTAL EXTAL XTAL C 2 74HC04 Fig.2. Clock applied conditions Fig. 3. Event count clock timing – 15 – CXP86608/86612/86616 = 4.5 to 5.5V, Vss = 0V reference) DD Min. Typ. Max 200 sys 20 32.768 – 0. ...
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... SCK input mode SO SCK output mode t KCY SIK KSI 0.8V Input data 0.2V t KSO 0.8V DD Output data 0.2V DD Fig. 4. Serial transfer timing – 16 – CXP86608/86612/86616 = 4.5 to 5.5V, Vss = 0V reference) DD Min. Max. 1000 8000/fc 400 4000/fc – 50 100 200 200 100 200 100 0. Unit ...
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... FEh to FFh and vice versa indicates the below values due to the contents of bit 6 ADC (CKS) of the A/D control register (ADC: 00F6h (CKS = "0"), fc/2 (CKS = "1") ADC V FT – 17 – CXP86608/86612/86616 = 4.5 to 5.5V, Vss = 0V reference) DD Min. Typ. Max. 8 ±3 – 4910 ...
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... INT0 INT1 INT2 (falling edge) RST (Ta = –20 to +75° 4.5 to 5.5V, Vss = 0V reference) DD Symbol Pins Conditions INT0 t IH INT1 t IL INT2 t RST RSL t IH 0.8V DD Fig. 6. Interruption input timing t RSL 0.2V DD Fig. 7. RST input timing – 18 – CXP86608/86612/86616 Min. Max. Unit 1 µs 32/fc µ 0.2V DD ...
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... Fig bus transfer timing device device SDA0 (or SDA1) SCL0 (or SCL1) 2 Fig device recommended circuit – 19 – CXP86608/86612/86616 = 4.5 to 5.5V, Vss = 0V reference) DD Conditions Min. Max. 0 4.7 4.0 4.7 4.0 4 250 4.7 t HD; STA t t SU; STO SU; STA Unit ...
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... C (pF) C (pF 10 12 12 16.0 Open Open 32.768kHz Content Non-existent – 20 – CXP86608/86612/86616 (iii) Sub clock TEX Circuit Rd (Ω) example ( (ii) 1 330 ( 120k (iii) Existent ...
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... V – Supply voltage [ 5V 25°C, Typical – System clock [MHz] Fig. 11. Characteristic curves – 21 – CXP86608/86612/86616 I vs 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode Sleep mode 10 15 ...
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... M 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL QFP-64P-L01 LEAD TREATMENT LEAD MATERIAL QFP064-P-1420 PACKAGE MASS – 22 – CXP86608/86612/86616 0° to 15° EPOXY RESIN SOLDER PLATING 42 ALLOY 8.6g + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.05 0° to10° EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g ...