EP910 ALTERA [Altera Corporation], EP910 Datasheet - Page 3

• Manufacturer Part Number: EP910
• Description: The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
Functional
Description
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For more information, see the
Development System & Software Data
The Classic architecture includes the following elements:
Macrocells
Classic macrocells, shown in
both sequential and combinatorial logic operation. Eight product terms
form a programmable-AND array that feeds an OR gate for combinatorial
logic implementation. An additional product term is used for
asynchronous clear control of the internal register; another product term
implements either an output enable or a logic-array-generated clock.
Inputs to the programmable-AND array come from both the true and
complement signals of the dedicated inputs, feedbacks from I/O pins that
are configured as inputs, and feedbacks from macrocell outputs. Signals
from dedicated inputs are globally routed and can feed the inputs of all
device macrocells. The feedback multiplexer controls the routing of
feedback signals from macrocells and from I/O pins. For additional
information on feedback select configurations, see
Figure 1. Classic Device Macrocell
Input, I/O, and
Feedbacks
Macrocell
Logic Array
Macrocells
Programmable registers
Output enable/clock select
Feedback select
Asynchronous Clear
To Logic Array
Figure
MAX+PLUS II Programmable Logic
Global
Clock
Sheet.
1, can be individually configured for
VCC
Classic EPLD Family Data Sheet
CLK
Feedback
OE
Select
CLR
Figure 3 on page
Q
Programmable
Output Enable/Clock Select
Register
749.
747