AS4LC4M16DG-5S/XT AUSTIN [Austin Semiconductor], AS4LC4M16DG-5S/XT Datasheet

AS4LC4M16DG-5S/XT

Manufacturer Part Number

AS4LC4M16DG-5S/XT

Description

4 MEG x 16 DRAM Extended Data Out (EDO) DRAM

Manufacturer

AUSTIN [Austin Semiconductor]

Datasheet

1.AS4LC4M16DG-5SXT.pdf (25 pages)

Current page: 1 of 25
Download datasheet (4Mb)

4 MEG x 16 DRAM

Extended Data Out (EDO) DRAM

FEATURES

• Single +3.3V ±0.3V power supply.

• Industry-standard x16 pinout, timing, functions, and

package.

• 12 row, 10 column addresses

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-compatible

• Extended Data-Out (EDO) PAGE MODE access

• 4,096-cycle CAS\-BEFORE-RAS\ (CBR) REFRESH

distributed across 64ms

• Optional self refresh (S) for low-power data retention

• Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020

OPTIONS

• Package(s)

• Timing

• Refresh Rates

• Operating Temperature Ranges

NOTE: The \ symbol indicates signal is active LOW.

*Contact factory for availability. Self refresh option available on IT

version only.

KEY TIMING PARAMETERS

AS4LC4M16

Rev. 1.1 6/05

-5

-6

50-pin TSOP (400-mil)

50ns access

60ns access

Standard Refresh

Self Refresh

Military (-55°C to +125°C)

Industrial (-40°C to +85°C)

104ns 60ns

84ns

50ns

20ns

25ns

Austin Semiconductor, Inc.

25ns

30ns

MARKINGS

None

-5

-6

13ns

15ns

10ns

8ns

Configuration

Refresh

Row Address

Column Addressing

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

For more products and information

www.austinsemiconductor.com

please visit our web site at

PIN ASSIGNMENT

50-Pin TSOP (DG)

(Top View)

AS4LC4M16

4 Meg x 16

A0-A11

A0-A9

DRAM

Related parts for AS4LC4M16DG-5S/XT

Related keywords

AS4LC4M16DG-5S/XT datasheet
AS4LC4M16DG-5S/XT data sheet
AS4LC4M16DG-5S/XT pdf datasheet
AS4LC4M16DG-5S/XT component
AS4LC4M16DG-5S/XT part
AS4LC4M16DG-5S/XT distributor
AS4LC4M16DG-5S/XT RoHS
AS4LC4M16DG-5S/XT datasheet download