YSS943 YAMAHA [YAMAHA CORPORATION], YSS943 Datasheet - Page 14

• Manufacturer Part Number: YSS943
• Description: ADAMB Advanced Digital Audio Multi channel decode processor
• Manufacturer: YAMAHA [YAMAHA CORPORATION]

14
(b) Runtime transfer mode
[Note]
Interruption of burst transfer:
• Burst transfer can be interrupted by setting nMICS to high level.
• The write operation becomes invalid when the rising edge of MISCK occurs for the 32nd bit of data (D31
• The MISO pin is set to high impedance (High-Z).
When the main decoder, noise generator, or impulse generator is used (PRGMOD[1:0] = 00, 01, or 10), the
coefficient data firmware can be downloaded in this mode. By using this mode, coefficients such as the
amount of 6-/7-/8-channel output delay can be changed without disruption of sound. The features of the
runtime transfer mode are as follows.
• Transfer is executed while decoding continues. Muting is not automatically effected during the transfer
• One word is transferred at a time while the device is handshaking with the microprocessor.
• Up to 32 words of transfer data are buffered and written all at once to the on-chip memory.
• Downloading coefficient firmware is supported.
<1> Start firmware download:
<2> Execute firmware download:
<3> Continuation of firmware download (if RDLEND = 0 in <2>):
<4> Termination of firmware download (if RDLEND = 1 in <2>):
[Note]
• Runtime transfer can be stopped by making nMICS high and clearing RDLMODE to 0.
• Start from <1> if non-successive addresses are transferred or when execution is started again after stopping
• When the transfer data is captured in the internal buffer, the value of RDLFLG automatically changes from
• Transfer successive address data in the order of the address data that has been incremented starting from
• Up to 32 words can be transferred as successive address data.
• The time until RDLFLG is automatically cleared to 0 after it has been set to 1 varies from 0 to 4 ms.
• Unlike the burst transfer mode, it is not necessary to change IACNFG and PRGMOD[1:0].
[Access steps and statuses]
in the figure).
period.
downloading.
1 to 0.
If RDLEND = 0 at this time, the transfer data is written only to the internal buffer and not to the transfer
destination address.
If RDLEND = 1, the transfer data, along with the data in the internal buffer, is sequentially written from
the transfer start address. If data of two or more words, such as filter coefficients, are changed at the
same time, transfer them as successive address data.
the data of the transfer start address.
If more than 32 words are transferred to successive addresses, start the next transfer from <1> after the
first 32 words have been transferred.
Set the runtime transfer mode and transfer start address by using registers.
• Initialize the handshake-related registers (RDLFLG = RDLEND = RDLCNT[4:0] = 0).
• Set the runtime transfer mode (RDLMODE = 1).
• Set the on-chip memory access start address IAA[20:0].
One word (32 bits) is downloaded at a time.
• Change the microprocessor interface pin function from register access to on-chip memory access (IA
• Fix nMICS to L.
• Transfer data with the LSB first and in 32-bit units.
• Raise nMICS from L to H.
• Read RDLCNT[4:0].
• Specify starting data transfer (RDLFLG = 1).
• Confirm the termination of data transfer (RDLFLG = 0).
• Return to step <2> above.
• Confirm the termination of data transfer/successive address transfer (RDLFLG = RDLEND = 0).
• Cancel the runtime transfer mode (RDLMODE = 0).
= 1). IAA[20:16] in this byte is valid only when it is set for the first time (for the second and
subsequent time, any value may be written).
Set RDLEND to 1 if the transferred data is the last word in successive address transfer; otherwise,
clear RDLEND to 0. At this time, write back the value that is read, to RDLCNT[4:0].
YSS944/943/940