YSS943 YAMAHA [YAMAHA CORPORATION], YSS943 Datasheet - Page 16

• Manufacturer Part Number: YSS943
• Description: ADAMB Advanced Digital Audio Multi channel decode processor
• Manufacturer: YAMAHA [YAMAHA CORPORATION]

CAE
16
(Chip 2, 3)
Internal signal
nMICS
Internal signal
nMICS (Chip 3)
n MICS
MI SI
(b) Microprocessor interface connection example 2 (multiple LSIs)
<1> A write operation to ChipAdr as the register access immediately after the falling edge of nMICS is
<2> A write operation to ChipAdr not immediately after the falling edge of nMICS is also invalid for chip
<3> The ChipAdr register can be read at any time. In this case, the write results from <1> are read from
<4> During on-chip memory access, register access for chip 3 is invalid.
<5> CAE of all LSIs becomes zero at the rising edge of nMICS.
[Note]
The timing by which the chip selection is confirmed in <1> is determined by the value of IOPORT3 to
IOPORT0 either at:
Once the chip selection is confirmed, the current value is retained until the next rising edge of nMICS.
Accordingly, even if the selected chip’s own IOPORT3 to IOPORT0 values change, the chip does not
become deselected immediately.
When nMICS is shared by multiple chips:
In the above cases, the multiple LSIs that share nMICS become the selected devices. In such cases,
multiple LSIs can be written to at once, but note with caution that a conflict can occur with the MISO output
when they are read.
(Chip 2)
• the register access immediately after falling edge of nMICS, or
• a write operation to ChipAdr.
• CAE = 0 at the register access immediately after the falling edge of nMICS or CAE = 1 is not written.
• CAE = 1 at the register access immediately after the falling edge of nMICS, but the values of IOPORT3
to IOPORT0 are the same for multiple LSIs.
valid to for all LSIs (chips 2 and 3 in this example) that share the nMICS pin. In this case, CAE = 1
and CA[3:0] = 3, so only the access only for chip 3 is valid.
3.
(Chip 2 is not affected by the register access itself.)
chip 3.
(Chip 2 is not affected by the register access itself.)
(Chip 2 is not affected by on-chip memory access.)
IOPORT3 to IOPORT0 = 2
nMICS
Chip 2
CA[3:0] = 0011
Write ChipAdr
CAE = 1
0
<1>
IOPORT3 to IOPORT0 = 3
Write ChipAdr
CA[3:0] = 0010
CAE = 1
<2>
Chip 3
Read ChipAdr
CA[3:0] = 0011
When multiple LSIs are connected such as on
the left, or when the device has a similar
interface, access is performed using the register
byte ChipAdr (CAE, CA[3:0]).
CAE = 1
<3>
1
YSS944/943/940
On-chip memory access
<4>
<5>
0