AX88780_07 ASIX [ASIX Electronics Corporation], AX88780_07 Datasheet - Page 12

• Manufacturer Part Number: AX88780_07
• Description: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

2.7 Miscellaneous
LINKLED
SPDLED
NA
TEST0
TEST1
XTLN
XTLP
RSTPB
IBREF_WESD
NC
2.8 Power/ground pin
Pin Name
VCC33
VCC25
GND
VCC25A
GNDA
Pin Name
Type
VCC3
VCC2
GND
VCC2
GND
IO3,
12mA,
PD
IO3,
12mA,
PD
I3
I3, PD
I3, PD
I25
O2
I25
I25
O
Type
1,13,40, 105, 119
4,20,27,35,57,60,64,72,78,107,117,123
8, 56, 73,106
81,85,89,96,98,100
Pin No.
82,86,87,92,95,99,101
55
54
51
52
53
90
91
97
88
67,68
Pin No.
This pin is tied to ground for normal operation.
25Mhz crystal or oscillator clock input. The recommended reference frequency is
25MHz crystal clock output. For 25MHz oscillator clock, this pin should be kept
Connect a 12.3Kohm resistor to ground.
In power-on reset phase, this pin will be latched by AX88780 to determine that system
operates in 32 or 16-bit mode. High state is 16-bit mode and low state is 32-bit mode.
The default is in 32-bit mode.
Upon finishing reset status, if bit11 of PHY_CTRL register is enabled, this pin stands
for:
Link: indicates a good link status, active low in 16-bit mode and active high in 32-bit
Traffic: indicates the traffic status and flashes while in TX or RX state.
In power-on reset phase, this pin will be latched by AX88780 to determine whether
AX88780 swaps the data or not. If the high state, AX88780 will swap the data
(big-endian). The default is little-endian.
Upon finishing reset stage, if bit12 PHY_CTRL register is enabled, this pin stands for
speed mode. In little-endian mode, low indicates that PHY is in 10BASE-TX mode,
and high state indicates PHY is in 100BASE-T mode. In big-endian mode, low
indicates that PHY is in 100Mbase-T mode and high state indicates PHY is in
10Base-TX mode. The speed indicator only works under bit12 of PHY_CTRL register
set by driver.
Pull down (by 4.7K) or floating for normal operation.
Pull down (by 4.7K) or floating for normal operation.
25Mhz +/- 0.005% (i.e. 25Mhz +/- 1250hz).
This input pin is only 2.5V tolerant and should not apply 3.3V clock signal directly to
this pin if an external oscillator is used.
floating.
Pull-up for normal operation.
No connection
Table 6: Miscellaneous signals group
Table 7: Power/Ground pins group
mode. The link indicator only works under bit11 of PHY_CTRL register set by
driver.
12
Pin Description
2.5V power for PHY analog part
Digital 3.3V power
Digital 2.5V power
Digital ground
Analog ground
ASIX ELECTRONICS CORPORATION
Pin Description
AX88780