AX88780_07 ASIX [ASIX Electronics Corporation], AX88780_07 Datasheet - Page 29
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AX88780_07
Manufacturer Part Number
AX88780_07
Description
High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet
1.AX88780_07.pdf
(55 pages)
4.31 GPIO_CTRL--GPIO Control Register
Offset Address = 0xFC8C
Field
31:10
9
8
7:2
1
0
Note: For output mode, software must firstly set the bit0 or bit1 to output mode then set bit8 or bit9.
4.32 RXINDICATOR--Receive Indicator Register
Offset Address= 0xFC90
Field
31:1
0
4.33 TXST--TX Status Register
Offset Address = 0xFC94
Field
31:4
3
2
1
0
RXSTART R/W
Name
TXD3FAIL R
TXD2FAIL R
TXD1FAIL R
TXD0FAIL R
Name
Name
GPIO1S
GPIO0S
GPIO1DIR R/W
GPIO0DIR R/W
-
-
-
-
Type
R
Type
R
Type
R
R/W
R/W
R
Default
All 0’s
0
All 0’s
Default
0
0
0
0
Default
All 0’s
0
0
All 0’s
1
1
Reserved
GPIO1 Status
This bit stands for the pin status of GPIO1 when it is set to input mode.
1 = high state
0 = low state
GPIO0 Status
This bit stands for the pin status of GPIO0 when it is set to input mode.
1 = high state
0 = low state
Reserved
GPIO1 Mode Direction
This field defines the direction of GPIO1 pin.
1 = input mode
0 = output mode
GPIO0 Mode Direction
This field defines the direction of GPIO pin.
1 = input mode
0 = output mode
Reserved
Receive Start
Driver set this bit to start or end receive operation from RX buffer of MAC.
1= Start read RX buffer
0= End read RX buffer
Reserved
TX Descriptor3 Transmit Fail
When this bit is set 1, it means MAC fails in transmission of descriptor 3.
This bit will be self-cleared when driver reads TXST register.
TX Descriptor2 Transmit Fail
When this bit is set 1, it means MAC fails in transmission of descriptor 2.
This bit will be self-cleared when driver reads TXST register.
TX Descriptor1 Transmit Fail
When this bit is set 1, it means MAC fails in transmission of descriptor 1.
This bit will be self-cleared when driver reads TXST register.
TX Descriptor0 Transmit Fail
When this bit is set 1, it means MAC fails in transmission of descriptor 0.
This bit will be self-cleared when driver reads TXST register.
Default = 0x0000_0000
Default = 0x0000_0000
Default = 0x0000_0003
29
Description
Description
Description
ASIX ELECTRONICS CORPORATION
AX88780