AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 35
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AX88796BLI
Manufacturer Part Number
AX88796BLI
Description
Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet
1.AX88796BLI.pdf
(82 pages)
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5.1.1 Command Register (CR)
Offset 00H (Read/Write)
Field
7:6
5:3
2
1
0
PS1, PS0 PS1, PS0: Page Select
TXP
START
Name
RD2,
RD1,
RD0
STOP
Description (Default = 21h)
The two bits select which register’s page is to be accessed.
It will be reset to default value when set PMR to D1 to D2 sleep state.
PS1
RD2, RD1, RD0: Remote DMA Command
These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88796B when a
Remote DMA has been completed. The Remote Byte Count should be cleared when a
Remote DMA has been aborted. The Remote Start Address is not restored to the starting
address if the Remote DMA is aborted.
It will be reset to default value when set PMR to D1 to D2 sleep state.
RD2 RD1 RD0
TXP: Transmit Packet
This bit could be set to initiate transmission of a packet
START:
This bit is used to active AX88796B operation.
This bit always read high when Host set once. It only clear by hardware or software reset.
STOP: Stop AX88796B
This bit is used to stop the AX88796B operation.
It will be reset to default value when set PMR to D1 to D2 sleep state.
0
0
1
1
0
0
0
0
1
0
0
1
1
X
PS0
0
1
0
1
0
1
0
1
X
page 0 (default)
page 1
page 2
page 3
Abort / Complete Remote DMA (default)
Not allowed
Remote Read
Remote Write
Not allowed
35
AX88796BLF / AX88796BLI
ASIX ELECTRONICS CORPORATION
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