K9K8G08U1M Samsung, K9K8G08U1M Datasheet
K9K8G08U1M
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K9K8G08U1M Summary of contents
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... K9K8G08U1M K9F4G08U0M Document Title 512M x 8 Bits / Bits NAND Flash Memory Revision History Revision No History 0.0 1. Initial issue The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office ...
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... Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package : - K9F4G08U0M-YCB0/YIB0 48 - Pin TSOP I ( 0.5 mm pitch) - K9F4G08U0M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I ( 0.5 mm pitch) - K9F4G08U0M-ICB0/IIB0 52 - Pin ULGA ( 1.00 mm pitch) - K9K8G08U1M-ICB0/IIB0 52 - Pin ULGA ( 1.00 mm pitch) 2 Advance FLASH MEMORY PKG Type TSOP1 52ULGA ...
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... K9K8G08U1M K9F4G08U0M PIN CONFIGURATION (TSOP1) K9F4G08U0M-YCB0,PCB0/YIB0,PIB0 N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 N N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8° 0.45~0.75 0.018~0.030 ...
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... K9K8G08U1M K9F4G08U0M PIN CONFIGURATION (ULGA / CLE PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View 12.00±0.10 #A1 K9F4G08U0M-ICB0/IIB0 / Vcc NC Vss IO7 IO5 Vcc R/B NC IO6 IO4 NC NC ...
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... K9K8G08U1M K9F4G08U0M /CE1 4 3 CLE1 PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View 12.00±0.10 #A1 K9K8G08U1M-ICB0/IIB0 /RE1 R/B2 IO7-2 NC IO6-2 IO5-2 Vcc /RE2 Vss IO7-1 IO5-1 Vcc R/B1 /WP2 IO6-1 IO4-1 /CE2 ...
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... K9K8G08U1M K9F4G08U0M PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
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... K9K8G08U1M K9F4G08U0M Figure 1. K9F4G08U0M Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2. K9F4G08U0M Array Organization 256K Pages (=4,096 Blocks) 2K Bytes ...
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... K9K8G08U1M K9F4G08U0M Product Introduction The K9F4G08U0M is a 4,224Mbit(4,429,185,024 bit) memory organized as 262,144 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo- dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... K9K8G08U1M K9F4G08U0M ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS K9F4G08U0M-XCB0 Temperature Under Bias K9F4G08U0M-XIB0 K9F4G08U0M-XCB0 Storage Temperature K9F4G08U0M-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins ...
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... Refer to the attached technical notes for appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed valid block, does not require Error Correction program/erase cycles Each K9F4G08U0M chip in the K9K8G08U1M has Maximun 80 invalid block. AC TEST CONDITION (K9F4G08U0M-XCB0 : 70° ...
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... K9K8G08U1M K9F4G08U0M Program / Erase Characteristics Parameter Program Time Dummy Busy Time for Two-Plane Page Program Number of Partial Program Cycles in the Same Page Block Erase Time NOTE : 1. Typical value is measured at Vcc=3.3V Typical program time is defined as the time that more than 50% of the whole pages are programmed at Vcc of 3.3V and temperature of 25°C within ...
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... K9K8G08U1M K9F4G08U0M AC Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High to Output Hold RE Low to Output Hold ...
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... K9K8G08U1M K9F4G08U0M NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9K8G08U1M K9F4G08U0M NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9K8G08U1M K9F4G08U0M NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. ...
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... K9K8G08U1M K9F4G08U0M NAND Flash Technical Notes Copy-Back Operation with EDC & Plane Definition for EDC Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has a bit error for charge loss or charge gain, accumulated copy-back operations could also accumulate bit errors. For this rea- son, two-bit ECC is recommanded for copy-back operation ...
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... K9K8G08U1M K9F4G08U0M System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption ...
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... K9K8G08U1M K9F4G08U0M NOTE I/O Device I/Ox K9F4G08U0M I I/O 7 Command Latch Cycle CLE CE WE ALE I/Ox Address Latch Cycle t CLS CLE ALS ALE t DS I/Ox Col. Add1 DATA Data In/Out Col. Add1 Col. Add2 2,112byte A0~A7 A8~A11 t t CLS CLH ...
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... K9K8G08U1M K9F4G08U0M Input Data Latch Cycle CLE ALE t ALS I/Ox DIN 0 * Serial Access Cycle after Read I/ R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. ...
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... K9K8G08U1M K9F4G08U0M Serial Access Cycle after Read REH RE t REA t CEA I/ R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz. ...
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... K9K8G08U1M K9F4G08U0M Read Operation CLE ALE RE I/Ox 00h Col. Add1 Col. Add2 Row Add1 Column Address R/B Read Operation (Intercepted by CE) CLE CE WE ALE RE I/Ox 00h Col. Add1 Col. Add2 Column Address R/B t CLR 30h Row Add2 Row Add3 ...
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... K9K8G08U1M K9F4G08U0M FLASH MEMORY 22 Advance ...
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... K9K8G08U1M K9F4G08U0M Page Program Operation CLE ALE RE I/Ox 80h Co.l Add1 Col. Add2 Row Add1 SerialData Column Address Input Command R/B NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle ADL Din ...
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... K9K8G08U1M K9F4G08U0M FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 24 Advance ≈ ...
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... K9K8G08U1M K9F4G08U0M FLASH MEMORY ≈ ≈ ≈ ≈ 25 Advance ...
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... K9K8G08U1M K9F4G08U0M BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h Row Add1 Row Add2 Row Add3 Row Address R/B Auto Block Erase Setup Command t t BERS WB D0h Busy Erase Command 26 Advance FLASH MEMORY 70h I/O 0 I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase 0 Command ...
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... K9K8G08U1M K9F4G08U0M ≈ ≈ FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 27 Advance ...
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... K9K8G08U1M K9F4G08U0M Two-Plane Block Erase Operation CLE ALE RE I/O 60h Row Add1 Row Add2 Row Add3 X Row Address R/B Block Erase Setup Command 2 times repeat * For Two-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Two-Plane Block Erase Operation ...
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... K9K8G08U1M K9F4G08U0M Read ID Operation CLE CE WE ALE RE I/Ox 90h Read ID Command Address 1cycle Device Device Code*(2nd Cycle) K9F4G08U0M K9K8G08U1M REA Device 00h ECh Code* Maker Code Device Code 3rd Cycle* DCh 10h Same as each K9F4G08U0M Advance FLASH MEMORY 3rd cyc.* 4th cyc ...
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... K9K8G08U1M K9F4G08U0M ID Definition Table Access command = 90H Description 1 st Byte Maker Code 2 Byte Device Code nd 3 Byte Internal Chip Number, Cell Type, Number of Simultaneously Programed Pages, Etc rd Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum 4 Byte th 3rd ID Data ...
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... K9K8G08U1M K9F4G08U0M Device Operation PAGE READ Read mode is initiated by writing 00h-30h to the command register along with five address cycles. In two consecutive read opera- tions, the second one doesn’t need 00h command, which five address cycles and 30h command initiates that operation. Once the command is latched, it does not need to be written for the following page read operation ...
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... K9K8G08U1M K9F4G08U0M Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 30h 5Cycles Col. Add.1,2 & Row Add.1,2,3 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2,112 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array(1time/16byte) ...
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... K9K8G08U1M K9F4G08U0M Figure 9. Random Data Input In a Page R/B I/Ox Address & Data Input 80h Col. Add.1,2 & Row Add1,2,3 Data Copy-Back Program The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben- efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block ...
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... K9K8G08U1M K9F4G08U0M EDC OPERATION Note that the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data input at the same address. Figure 12. Page Copy-Back program Operation with EDC & ...
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... K9K8G08U1M K9F4G08U0M Figure 14. Two-Plane Page Program R/B I 80h Address & Data Input Valid Fixed ’Low’ Fixed ’Low’ Fixed ’Low’ NOTE : It is noticeable that same row address except for A 80h Data Input Plane 0 ...
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... K9K8G08U1M K9F4G08U0M Two-Plane Copy-Back Page Program Two-Plane Copy-Back Page Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous pro- gramming of two pages ...
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... K9K8G08U1M K9F4G08U0M Figure 17. Two-Plane Copy-Back program Operation with Random Data Input R/B I/Ox Add.(5Cycles) 00h 35h Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane0 R/B I/Ox Add.(5Cycles) 85h Col. Add.1,2 & Row Add.1,2,3 1 Destination Address Valid Fixed ’Low’ Fixed ’ ...
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... K9K8G08U1M K9F4G08U0M READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
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... Device Device Code*(2nd Cycle) K9F4G08U0M K9K8G08U1M RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased ...
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... K9K8G08U1M K9F4G08U0M READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9K8G08U1M K9F4G08U0M Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit gets ready for any command sequences as shown in Figure 21 ...