CH7301A-T-A ETC [List of Unclassifed Manufacturers], CH7301A-T-A Datasheet - Page 22

• Manufacturer Part Number: CH7301A-T-A
• Description: Chrontel CH7301 DVI Output Device
• Manufacturer: ETC [List of Unclassifed Manufacturers]

CHRONTEL
22
DAC Control Register
Bit 0 of register DC selects the DAC bypass mode. A value of ‘1’ outputs the incoming data directly at the
DAC[2:0] outputs.
Bits 2-1 of register DC control the DAC gain. DACG0 should be set low for NTSC and PAL-M video standards,
and high for PAL and NTSC-J video standards. DACG1 should be low when the input data format is RGB (IDF =
0-3), and high when the input data format is YCrCb (IDF = 4).
Bits 4-3 of register DC select the signal to be output from the C/H Sync pin according to Table 9 below.
Table 9: Composite / Horizontal Sync Output
Buffered Clock Output Register
Bits 2-0 of register BCO select the signal output at the BCO pin, according to Table 10 below:
Table 10: BCO Output Signal
Bit 3 of register BCO selects the polarity of the BCO output. A value of ‘1’ does not invert the signal at the output
pad.
Bit 4 of register BCO enables the BCO output. When BCOEN is high, the BCO pin will output the selected signal.
When BCOEN is low, the BCO pin will be held in tri-state mode.
DEFAULT:
DEFAULT:
SYNCO[1:0]
00
01
10
11
BCO[2:0]
000
001
010
011
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
Reserved Reserved
Reserved Reserved Reserved BCOEN
Buffered Clock Output
(Not Valid)
(Not Valid)
(Not Valid)
(Not Valid)
C/H Sync Output
No Output
VGA Horizontal Sync
TV Composite Sync (Not Valid)
TV Horizontal Sync
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
(Not Valid)
R/W
5
5
0
SYNCO1 SYNCO0
BCO[2:0]
100
101
110
111
R/W
R/W
4
0
4
0
BCOP
R/W
R/W
Buffered Clock Output
(Not Valid)
(Not Valid)
VGA Vertical Sync
(Not Valid)
3
0
3
0
DACG1
BCO2
201-0000-036 Rev 1.1, 3/20/2000
R/W
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
0
2
0
DACG0
BCO1
R/W
R/W
CH7301A
1
0
1
0
DC
21h
6
BCO
22h
8
DACBP
BCO0
R/W
R/W
0
0
0
0