CH7301A-T-A ETC [List of Unclassifed Manufacturers], CH7301A-T-A Datasheet - Page 4

• Manufacturer Part Number: CH7301A-T-A
• Description: Chrontel CH7301 DVI Output Device
• Manufacturer: ETC [List of Unclassifed Manufacturers]

CHRONTEL
4
Table 1: Pin Description
64-Pin
LQFP
22, 21
25, 24
28, 27
30, 31
35
37
38
39
43
46
47
48
50 – 55,
58 – 63
57, 56
1, 12, 49
6, 11, 64
45
23, 29
20, 26, 32
18, 44
16, 17, 41,42 4
33
34, 36, 40
# Pins
2
2
2
2
1
1
1
1
1
1
1
1
12
2
3
3
1
2
3
2
1
3
Type
Out
Out
Out
Out
In
Out
Out
Out
Out
Out
Out
In
In
Power
Power
Power
Power
Power
Power
Power
Power
Power
Symbol
TDC0,
TDC0*
TDC1,
TDC1*
TDC2,
TDC2*
TLC,
TLC*
ISET
G
R
B
NC
TLDET*
BCO
C/H SYNC
D[11] - D[0]
XCLK,
XCLK*
DVDD
DGND
DVDDV
TVDD
TGND
AVDD
AGND
VDD
GND
Description
TMDS
These pins provide the TMDS
channel 0 (blue).
TMDS
These pins provide the TMDS
channel 1 (green).
TMDS
These pins provide the TMDS
channel 2 (red).
TMDS
These pins provide the differential clock output for the
TMDS
outputs.
Current Set Resistor Input
This pin sets the DAC current. A 140 ohm resistor should be
connected between this pin and GND (DAC ground) using
short and wide traces.
Green Output
Red Output
Blue Output
No Connect
DVI Link Detect Output
This pin provides an open drain output which pulls low when a
termination change has been detected on the HPDET input.
The output is released through IIC control.
Buffered Clock Output
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO
register.
Composite / Horizontal Sync Output
This pin is only for use with the TV-Out function.
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video
port of a graphics controller. The levels are 0 to DVDDV,
and the VREF signal is used as the threshold level.
External Clock Inputs
These inputs form a differential clock signal input to the
CH7301 for use with the H, V, DE and D[11:0] data. If
differential clocks are not available, the XCLK* input
should be connected to VREF.
The output clocks from this pad cell are able to have their
polarities reversed under the control of the MCP bit.
Digital Supply Voltage
Digital Ground
I/O Supply Voltage
DVI Transmitter Supply Voltage
DVI Transmitter Ground
PLL Supply Voltage
PLL Ground
DAC Supply Voltage
DAC Ground
TM
TM
TM
TM
TM
interface corresponding to data on the TDC[0:2]
Data Channel 0 Outputs
Data Channel 1 Outputs
Data Channel 2 Outputs
Link Clock Outputs
(3.3V - 1.1V)
(3.3V)
(3.3V)
(3.3V)
201-0000-036 Rev 1.1, 3/20/2000
TM
TM
TM
differential outputs for data
differential outputs for data
differential outputs for data
(3.3V)
CH7301A