K9F6408U0M-TIB0 Samsung semiconductor, K9F6408U0M-TIB0 Datasheet - Page 22

• Manufacturer Part Number: K9F6408U0M-TIB0
• Description: 8M x 8 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

PAGE PROGRAM
R/B
I/O
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A
page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, fol-
lowed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can
be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80H), followed by the three cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10H) initiates the programming process. Writing 10H alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with
RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or
the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7). The internal write verify
detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command
mode until another valid command is written to the command register.
Figure 6. Sequential Row Read2 Operation(SE=fixed low)
Figure 7. Program & Read Status Operation
K9F6408U0M-TCB0, K9F6408U0M-TIB0
R/B
I/O
0
0
~
~
7
7
80H
50H
(A
Don t Care)
4
~ A
A
Address & Data Input
0
7
A
528 Byte Data
Start Add.(3Cycle)
:
~ A
0
~ A
7
& A
3
& A
9
~ A
9
~ A
22
22
t
R
1st half array
10H
Data Field
Data Output
1st
2nd half array
22
t
Spare Field
PROG
t
R
1st
2nd
Nth
Data Output
(16 Byte)
70H
2nd
FLASH MEMORY
t
R
I/O
Fail
0
Data Output
(16 Byte)
Nth
Pass