ADIS16480 AD [Analog Devices], ADIS16480 Datasheet - Page 10

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ADIS16480

Manufacturer Part Number
ADIS16480
Description
Ten Degrees of Freedom Inertial Sensor
Manufacturer
AD [Analog Devices]
Datasheet

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ADIS16480
BASIC OPERATION
The
on its own when it has a valid power supply. After running through
its initialization process, it begins sampling, processing, and
loading calibrated sensor data into the output registers, which
are accessible using the SPI port. The SPI port typically connects to
a compatible port on an embedded processor, using the connection
diagram in Figure 11. The four SPI signals facilitate synchronous,
serial data communication. Connect RST (see Table 5) to VDD
or leave it open for normal operation. The factory default
configuration provides users with a data-ready signal on the
DIO2 pin, which pulses high when new data is available in
the output data registers.
Table 6. Generic Master Processor Pin Names and Functions
Mnemonic
SS
IRQ
MOSI
MISO
SCLK
Embedded processors typically use control registers to configure
their serial ports for communicating with SPI slave devices
such as the ADIS16480. Table 7 provides a list of settings, which
describe the SPI protocol of the ADIS16480. The initialization
routine of the master processor typically establishes these settings
using firmware commands to write them into its serial control
registers.
Table 7. Generic Master Processor SPI Settings
Processor Setting
Master
SCLK ≤ 15 MHz
SPI Mode 3
MSB-First Mode
16-Bit Mode
SYSTEM
PROCESSOR
SPI MASTER
ADIS16480
VDD
Figure 11. Electrical Connection Diagram
is an autonomous sensor system that starts up
I/O LINES ARE COMPATIBLE WITH
SCLK
MOSI
MISO
IRQ
SS
Function
Slave select
Interrupt request
Master output, slave input
Master input, slave output
Serial clock
Description
The
Maximum serial clock rate
CPOL = 1 (polarity), and CPHA = 1 (phase)
Bit sequence
Shift register/data length
3.3V LOGIC LEVELS
ADIS16480
6
3
5
4
9
operates as a slave
CS
SCLK
DIN
DOUT
DIO2
10
13
11
+3.3V
ADIS16480
14
12
15
23
Rev. 0 | Page 10 of 40
REGISTER STRUCTURE
The register structure and SPI port provide a bridge between
the sensor processing system and an external, master processor.
It contains both output data and control registers. The output
data registers include the latest sensor data, a real-time clock, error
flags, alarm flags, and identification data. The control registers
include sample rate, filtering, input/output, alarms, calibration,
EKF tuning, and diagnostic configuration options. All
communication between the
processor involves either reading or writing to one of the user
registers.
The register structure uses a paged addressing scheme that is
composed of 13 pages, with each one containing 64 register
locations. Each register is 16 bits wide, with each byte having
its own unique address within that page’s memory map. The SPI
port has access to one page at a time, using the bit sequence in
Figure 17. Select the page to activate for SPI access by writing
its code to the PAGE_ID register. Read the PAGE_ID register
to determine which page is currently active. Table 8 displays the
PAGE_ID contents for each page, along with their basic functions.
The PAGE_ID register is located at Address 0x00 on every page.
Table 8. User Register Page Assignments
Page
0
1
2
3
4
5
6
7
8
9
10
11
12
SENSOR
TRIAXIS
TRIAXIS
TRIAXIS
ACCEL
MAGN
GYRO
BARO
TEMP
PAGE_ID
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
Function
Output data, clock, identification
Reserved
Calibration
Control: sample rate, filtering, I/O, alarms
Serial number
FIR Filter Bank A Coefficient 0 to Coefficient 59
FIR Filter Bank A, Coefficient 60 to Coefficient 119
FIR Filter Bank B, Coefficient 0 to Coefficient 59
FIR Filter Bank B, Coefficient 60 to Coefficient 119
FIR Filter Bank C, Coefficient 0 to Coefficient 59
FIR Filter Bank C, Coefficient 60 to Coefficient 119
FIR Filter Bank D, Coefficient 0 to Coefficient 59
FIR Filter Bank D, Coefficient 60 to Coefficient 119
Figure 12. Basic Operation
CONTROLLER
ADIS16480
DSP
REGISTERS
REGISTERS
CONTROL
OUTPUT
and an external
Data Sheet

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