SI5351A-A-GMR Silicon Laboratories, SI5351A-A-GMR Datasheet - Page 15

• Manufacturer Part Number: SI5351A-A-GMR
• Description: Control: I2C; Reference Inputs: 1; Clock Outputs: 8; Input Frequency (MHz): 25/27 MHz (Xtal); Output Frequency (MHz):...
• Manufacturer: Silicon Laboratories

A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 10.
AC and DC electrical specifications for the SCL and SDA pins are shown in Table 7. The timing specifications and
timing diagram for the I
with SMBus interfaces.
2
C bus is compatible with the I
Read Operation – Single Byte
Read Operation - Burst (Auto Address Increment)
S
S
S
S
Write Operation – Single Byte
Write Operation - Burst (Auto Address Increment)
S
S
Slv Addr [6:0]
Slv Addr [6:0]
Slv Addr [6:0]
Slv Addr [6:0]
From slave to master
From master to slave
Slv Addr [6:0]
Slv Addr [6:0]
From slave to master
From master to slave
Figure 10. I
Figure 9. I
0 A Reg Addr [7:0]
1 A
0 A Reg Addr [7:0]
1 A
0 A Reg Addr [7:0]
0 A Reg Addr [7:0]
Preliminary Rev. 0.95
Data [7:0]
Data [7:0] A
2
2
C Write Operation
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
C Read Operation
2
C-Bus Standard. SDA timeout is supported for compatibility
N
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
A P
A P
P
Data [7:0]
Reg Addr +1
A Data [7:0]
A Data [7:0] A Data [7:0]
N
P
A
Reg Addr +1
P
A
P
Si5351A/B/C
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