SI5351A-A-GMR Silicon Laboratories, SI5351A-A-GMR Datasheet - Page 60

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SI5351A-A-GMR

Manufacturer Part Number
SI5351A-A-GMR
Description
Control: I2C; Reference Inputs: 1; Clock Outputs: 8; Input Frequency (MHz): 25/27 MHz (Xtal); Output Frequency (MHz):...
Manufacturer
Silicon Laboratories
Datasheet
Si5351A/B/C
Reset value = 0000 0000
Reset value = 0000 0000
Reset value = 0000 0000
60
Register 168. CLK3 Initial Phase Offset
Register 169. CLK4 Initial Phase Offset
Register 170. CLK5 Initial Phase Offset
Name
6:0
Name
6:0
Name
6:0
Bit
Bit
Bit
Type
Type
Type
7
7
7
Bit
Bit
Bit
CLK3_PHOFF[6:0] Clock 3 Initial Phase Offset.
CLK4_PHOFF[6:0] Clock 4 Initial Phase Offset.
CLK5_PHOFF[6:0] Clock 5 Initial Phase Offset.
Reserved
Reserved
Reserved
R/W
R/W
R/W
Name
Name
Name
D7
D7
D7
R/W
R/W
R/W
D6
D6
D6
Only write 0 to this bit.
CLK3_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
Only write 0 to this bit.
CLK4_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
Only write 0 to this bit.
CLK5_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
R/W
R/W
R/W
D5
D5
D5
Preliminary Rev. 0.95
R/W
R/W
R/W
D4
D4
D4
CLK3_PHOFF[6:0]
CLK4_PHOFF[6:0]
CLK5_PHOFF[6:0]
R/W
Function
R/W
Function
R/W
Function
D3
D3
D3
R/W
R/W
R/W
D2
D2
D2
R/W
R/W
R/W
D1
D1
D1
R/W
R/W
R/W
D0
D0
D0

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