IS61C512-35TI ETC-unknow, IS61C512-35TI Datasheet - Page 4

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IS61C512-35TI

Manufacturer Part Number
IS61C512-35TI
Description
64k X 8 High-speed Cmos Static Ram
Manufacturer
ETC-unknow
Datasheet
IS61C512
READ CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
AC TEST LOADS
4
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
and output loading specified in Figure 1a.
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
RC
AA
OHA
ACE
ACE
DOE
LZOE
HZOE
LZCE
LZCE
HZCE
PU
PD
(3)
(3)
1
2
1
2
OUTPUT
(2)
(2)
(2)
(2)
(2)
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE1 to Low-Z Output
CE2 to Low-Z Output
CE1 or CE2 to High-Z Output
CE1 or CE2 to Power-Up
CE1 or CE2 to Power-Down
3.3V
Including
100 pF
jig and
scope
Figure 1a.
1213 Ω
1378 Ω
See Figures 1a and 1b
Min.
15
0
0
2
2
0
0
3
-15 ns
0V to 3.0V
Max.
15
15
15
12
1.5V
Unit
3 ns
7
6
8
OUTPUT
3.3V
Min.
20
3
0
0
3
3
0
0
(1)
-20 ns
Including
(Over Operating Range)
jig and
Max.
scope
20
20
20
18
5 pF
9
9
Figure 1b.
8
1213 Ω
Min.
25
0
0
0
0
3
3
3
-25 ns
1378 Ω
Max.
25
25
25
10
10
20
9
Integrated Circuit Solution Inc.
Min.
35
0
0
0
0
3
3
3
-35 ns
Max.
35
35
35
12
12
20
12
SR011-0B
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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