IS61C512-35TI ETC-unknow, IS61C512-35TI Datasheet - Page 6

• Manufacturer Part Number: IS61C512-35TI
• Description: 64k X 8 High-speed Cmos Static Ram
• Manufacturer: ETC-unknow

IS61C512
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE
6
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
4. Tested with OE HIGH.
Symbol
t
t
t
t
t
t
t
t
t
t
t
and output loading specified in Figure 1a.
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
WC
SCE
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
1
2
(4)
(2)
(2)
ADDRESS
Parameter
Write Cycle Time
CE1 to Write End
CE2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
D
CE1
CE2
OUT
WE
D
IN
WE
WE
WE Controlled)
WE
t
DATA UNDEFINED
SA
Min.
15
12
12
12
10
—
0
0
8
0
2
-15 ns
Max.
(1,2)
—
—
—
—
—
—
—
—
—
—
7
t
AW
t
HZWE
t
t
SCE1
SCE2
t
WC
t
Min.
PWE
20
15
15
15
12
10
—
0
0
0
2
-20 ns
HIGH-Z
(1,3)
Max.
—
—
—
—
—
—
—
—
—
10
—
(Over Operating Range)
t
SD
DATA-IN VALID
Min.
25
20
20
20
15
12
—
0
0
0
2
t
HA
-25 ns
t
t
LZWE
HD
Max.
12
—
—
—
—
—
—
—
—
—
—
Integrated Circuit Solution Inc.
Min.
35
30
30
30
20
15
—
0
2
0
0
-35 ns
Max.
—
—
—
—
—
—
—
—
—
—
8
SR011-0B
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns