A42MX09-1TQG176M Microsemi, A42MX09-1TQG176M Datasheet - Page 18

• Manufacturer Part Number: A42MX09-1TQG176M
• Description: Ic Fpga Mx Sgl Chip 14k 176-Tqfp
• Manufacturer: Microsemi

C
To calculate the active power dissipated from the
complete design, the switching frequency of each part of
the logic must be known. The equation below shows a
piece-wise linear summation over all components.
where:
1 -1 4
Modules (C
Input Buffers (C
Output Buffers (C
Routed Array Clock Buffer Loads (C
m
n
p
q
q
r
r
C
C
C
C
C
f
f
f
f
f
1
2
m
n
p
q1
q2
EQ
1
2
40MX and 42MX Automotive FPGA Families
EQM
EQI
EQO
EQCR
L
0.5 * (q
0.5 * (q
(n * C
Values for Actel MX FPGAs
= Number of logic modules switching at frequency f
= Number of input buffers switching at frequency f
= Number of output buffers switching at frequency f
= Number of clock loads on the first routed array
= Number of clock loads on the second routed array
= Fixed capacitance due to first routed array clock
= Fixed capacitance due to second routed array clock
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers in pF
= Equivalent capacitance of routed array clock in pF
= Output load capacitance in p
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in MHz
Power = V
1
2
EQI
* C
clock
clock
* C
EQM
* f
EQCR
EQI
EQCR
)
n
EQO
)
)
Inputs
CCA
* f
)
* f
2
q1
q2
* [(m x C
+ (p * (C
)
routed_Clk1
)
routed_Clk2
EQO
EQM
+ (r
+ (r
+ C
* f
EQCR
1
2
m
L
* f
) * f
)
* f
Modules
)
q1
q2
p
)
routed_Clk1
)
)
outputs
routed_Clk2
+
3.5
6.9
18.2
1.4
+
EQ 1-2
+
n
m
p
v3.1
Fixed Capacitance Values
for MX FPGAs (pF)
Determining Average Switching
Frequency
To determine the switching frequency for a design, the
data input values to the circuit must be clearly
understood. The following guidelines represent worst-
case scenarios; these can be used to generally predict the
upper limits of power dissipation.
Device Type
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Logic Modules (m)
Inputs Switching (n)
Outputs Switching (p)
First Routed Array Clock Loads (q
Second Routed Array Clock Loads
(q
Load Capacitance (C
Average Logic Module Switching
Rate (f
Average Input Switching Rate (f
Average Output Switching Rate (f
Average First Routed Array Clock
Rate (f
Average Second Routed Array Clock
Rate (f
2
)
m
q1
q2
)
)
)
L
)
routed_Clk1
n
)
1
p
)
)
41.4
68.6
118
165
185
220
r1
=
=
=
=
=
=
=
=
=
=
=
80% of
Combinatorial
Modules
# of Inputs/4
# of Outputs/4
40% of Sequential
Modules
40% of Sequential
Modules
35 pF
F/10
F/5
F/10
F
F/2
routed_Clk2
118
165
185
220
N/A
N/A
r2