ATMEGA8-16AI SL383 Atmel, ATMEGA8-16AI SL383 Datasheet - Page 130

• Manufacturer Part Number: ATMEGA8-16AI SL383
• Description: Semiconductors and Actives, Microprocessors, Microcontrollers
• Manufacturer: Atmel

130
ATmega8(L)
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
rized below:
Table 48. CPOL Functionality
• Bit 2 – CPHA: Clock Phase
The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
tionality is summarized below:
Table 49. CPHA Functionality
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 50. Relationship Between SCK and the Oscillator Frequency
SPI2X
CPOL
CPHA
0
0
0
0
1
1
1
1
0
1
0
1
Figure 59
SPR1
0
0
1
1
0
0
1
1
Leading Edge
Leading Edge
and
Sample
Falling
Rising
Setup
Figure 60
Figure 59
SPR0
0
1
0
1
0
1
0
1
for an example. The CPOL functionality is summa-
and
Figure 60
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
for an example. The CPHA func-
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
2486W–AVR–02/10
osc
is