MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 71
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MT46V64M16P-6T IT:A
Manufacturer Part Number
MT46V64M16P-6T IT:A
Description
DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
Manufacturer
Micron
Datasheet
1.MT46V64M16P-6TITA.pdf
(82 pages)
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Figure 43:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Command
Address
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-PRECHARGE – Uninterrupting
Notes:
Bank a,
WRITE
Col b
T0
t DQSS
t DQSS
t DQSS
1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE
6. A10 is LOW with the WRITE command (auto precharge is disabled).
t
and WRITE commands may be to different devices, in which case
the PRECHARGE command could be applied earlier.
DI
b
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
DI
T1
b
DI
b
T1n
NOP
T2
T2n
71
NOP
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t WR
NOP
T4
1Gb: x4, x8, x16 DDR SDRAM
Transitioning Data
(a or all)
Bank,
T5
PRE
©2000 Micron Technology, Inc. All rights reserved.
t
WR is not required, and
t RP
T6
NOP
Operations
Don’t Care
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