DS2153QN-A7 Maxim Integrated, DS2153QN-A7 Datasheet - Page 20
DS2153QN-A7
Manufacturer Part Number
DS2153QN-A7
Description
In Stock
Manufacturer
Maxim Integrated
Datasheet
1.DS2153QA7.pdf
(60 pages)
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SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex)
5.1 CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is
cleared when the DS2153Q has successfully obtained synchronization at the CRC4 level. The counter can
also be cleared by disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the
amount of time the DS2153Q has been searching for synchronization at the CRC4 level. Annex B of
CCITT G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then
the search should be abandoned and proper action taken. The CRC4 sync counter will rollover.
(MSB)
CSC5
SYMBOL
CRC4SA
CASSA
FASSA
CSC5
CSC4
CSC3
CSC2
CSC0
CSC4
POSITION
SSR.7
SSR.6
SSR.5
SSR.4
SSR.3
SSR.2
SSR.1
SSR.0
CSC3
NAME AND DESCRIPTION
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CRC4 Sync Counter Bit 4.
CRC4 Sync Counter Bit 3.
CRC4 Sync Counter Bit 2.
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next
to LSB bit is not accessible. This bit will toggle each time the
CRC4 MF search times out at 8ms.
FAS Sync Active. Set while the synchronizer is searching for
alignment at the FAS level.
CAS MF Sync Active. Set while the synchronizer is searching
for the CAS MF alignment word.
CRC4 MF Sync Active. Set while the synchronizer is searching
for the CRC4 MF alignment word.
CSC2
20 of 60
CSC0
FASSA
CASSA
CRC4SA
(LSB)
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