DS2153QN-A7 Maxim Integrated, DS2153QN-A7 Datasheet - Page 56
DS2153QN-A7
Manufacturer Part Number
DS2153QN-A7
Description
In Stock
Manufacturer
Maxim Integrated
Datasheet
1.DS2153QA7.pdf
(60 pages)
- Current page: 56 of 60
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Table 16-2. AC Characteristics—Receive Side
(V
DS2153QN.) (See
NOTES:
1) Jitter attenuator enabled in the receive side path.
2) Jitter attenuator disabled or enabled in the transmit path.
3) SYSCLK = 1.544MHz.
4) SYSCLK = 2.048MHz.
ACLKI/RCLK Period
RCLK Pulse Width
RCLK Pulse Width
SYSCLK Period
SYSCLK Pulse Width
RSYNC Setup to SYSCLK
Falling
RSYNC Pulse Width
SYSCLK Rise/Fall Times
Delay RCLK or SYSCLK to
RSER Valid
Delay RCLK or SYSCLK to
RCHCLK
Delay RCLK or SYSCLK to
RCHBLK
Delay RCLK or SYSCLK to
RSYNC
Delay RCLK to RLCLK
Delay RCLK to RLINK Valid
DD
= 5V ±5%, T
PARAMETER
A
Figure
= 0°C to +70°C for DS2153Q; V
16-4.)
SYMBOL
t
t
R
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PW
CH
CH
DD
CP
CL
CL
SH
SL
SU
D1
D2
D3
D4
D5
SP
SP
, t
F
MIN
56 of 60
180
180
200
90
50
50
25
50
DD
= 5V +5%/-4%, T
TYP
488
244
244
244
244
648
488
MAX
t
SH
25
70
50
50
50
50
50
-5
A
= -40°C to +85°C for
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
2
3
4
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