AD60003RSZ24 Analog Devices, AD60003RSZ24 Datasheet - Page 12

• Manufacturer Part Number: AD60003RSZ24
• Description: The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming...
• Manufacturer: Analog Devices

AD807
USING THE AD807
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
Use of a 10 F capacitor between V
mended. Care should be taken to isolate the 5 V power trace to
V
the CLKOUT and DATAOUT signals.
Use of 0.1 F capacitors between IC power supply and ground
is recommended. Power supply decoupling should take place as
close to the IC as possible. Refer to the schematic, Figure 12,
for recommended connections.
Transmission Lines
Use of 50
CLKOUT, and DATAOUT signals.
Terminations
Termination resistors should be used for PIN, NIN, CLKOUT,
and DATAOUT signals. Metal, thick film, 1% tolerance resistors
are recommended. Termination resistors for the PIN, NIN signals
should be placed as close as possible to the PIN, NIN pins.
Connections from 5 V to load resistors for PIN, NIN, CLKOUT,
and DATAOUT signals should be individual, not daisy chained.
This will avoid crosstalk on these signals.
Loop Damping Capacitor, C
A ceramic capacitor may be used for the loop damping capaci-
tor. Using a 0.15 F, +20% capacitor for a damping factor of
five provides < 0.1 dB jitter peaking.
CC2
(Pin 3). The V
transmission lines are recommended for PIN, NIN,
CC2
pin is used inside the device to provide
D
CC
0.1574 (4.00)
0.1497 (3.80)
and ground is recom-
0.0098 (0.25)
0.0040 (0.10)
PIN 1
16
1
0.050 (1.27)
16-Lead Small Outline IC Package
0.3937 (10.00)
Dimensions shown in inches and (mm).
0.3859 (9.80)
BSC
0.0192 (0.49)
0.0138 (0.35)
OUTLINE DIMENSIONS
0.0688 (1.75)
0.0532 (1.35)
9
8
(R-16A)
SEATING
PLANE
0.2440 (6.20)
0.2284 (5.80)
AD807 Output Squelch Circuit
A simple P-channel FET circuit can be used in series with the
Output Signal ECL Supply (V
data outputs when SDOUT indicates a loss of signal (Figure 20).
The V
ECL loads, plus 5 mA for all 4 ECL output stages). This means
that selection of a FET with ON RESISTANCE of 0.5
affect the common mode of the ECL outputs by only 31 mV.
0.0099 (0.25)
0.0075 (0.19)
CC2
supply pin draws roughly 61 mA (14 mA for each of 4
8
0
0.0196 (0.50)
0.0099 (0.25)
BYPASS
0.0500 (1.27)
0.0160 (0.41)
5V
CAP
P_FET
45
1
2
3
4
5
6
7
8
DATAOUTN
DATAOUTP
V
CLKOUTN
CLKOUTP
V
CF1
CF2
CC2
CC1
TO V
CC2
AD807
, Pin 3) to squelch clock and
CC1
, AV
THRADJ
CC
SDOUT
AV
AV
AV
, AV
V
CC2
PIN
NIN
CC1
EE
EE
CC2
16
15
14
13
12
11
10
9
will