83115BRLFT IDT, 83115BRLFT Datasheet
83115BRLFT
Specifications of 83115BRLFT
Related parts for 83115BRLFT
83115BRLFT Summary of contents
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... OE1 GND IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER Features • Sixteen LVCMOS / LVTTL outputs, 15 • One LVCMOS / LVTTL clock input • Maximum output frequency: 200MHz • All inputs are 5V tolerant • Output skew: 250ps (maximum) • ...
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... PULLDOWN Power Dissipation Capacitance C PD (per output); NOTE 1 R Output Impedance OUT IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER Type Description Output enable pin. When LOW, forces outputs Q[2:7] to Hi-Z state. Input Pullup 5V tolerant. LVCMOS/LVTTL interface levels. See Table 3. Single-ended clock outputs. 15 Output LVCMOS/LVTTL interface levels ...
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... Outputs Package Thermal Impedance, θ JA Storage Temperature, T STG DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, V Symbol Parameter V Positive Supply Voltage DD I Power Supply Current DD IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER Control OE2 Control OE1 OE2 Q[0:1], Q[14:15] 0 Hi-Z 1 Active 0 Hi-Z 1 Active 0 Hi-Z 1 Active ...
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... NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER = 3.3V ± 5 ...
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... Often the noise floor of the equipment is higher than the noise floor of the IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental ...
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... Par Par tsk(pp) Part-to-Part Skew 80% 20% Q0:Q15 t R Output Rise/Fall Time IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER SCOPE Output Skew CLK Q0:Q15 Propagation Delay Q0:Q15 80% 20 Output Duty Cycle/Pulse Width/Period 6 tsk(o) V ...
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... JA Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS83115: 985 IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. θ ...
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... Package Outline - G Suffix for 28 Lead SSOP Table 7. Package Dimensions for 28 Lead SSOP All Dimensions in Millimeters Symbol Minimum Maximum 1. 0.20 c 0.18 D 9.80 10.00 E 5.80 E1 3.80 e 0.635 Basic L 0.40 α 0° ZD 0.84 Ref Reference Document: JEDEC Publication 95, MO-137 IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 1.75 0.25 1.50 0.30 0.25 6.20 4.00 1.27 8° 8 ICS83115BR REV. C MARCH 14, 2008 ...
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... ICS83115BR ICS83115BRLF ICS83115BRLF ICS83115BRLFT ICS83115BRLF NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...
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... LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER Revision History Sheet Rev Table Page Description of Change Characteristics Table - changed Output Rise/Fall Time limits from C 650ps min./1150ps max. to 400ps min./800ps max. IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 10 ICS83115BR REV. C MARCH 14, 2008 Date 3/14/08 ...
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... U.S.) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered www ...