8534BMI-13LF IDT, 8534BMI-13LF Datasheet

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8534BMI-13LF

Manufacturer Part Number
8534BMI-13LF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 8534BMI-13LF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS8534BMI-13LF
General Description
The ICS8534-01 is a low skew, 1-to-22 Differential-to-3.3V LVPECL
Fanout Buffer. The ICS8534-01 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input levels.
The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input
levels. The device is internally synchronized to eliminate runt pulses
on the outputs during asynchronous assertion/deassertion of the OE
pin. The ICS8534-01’s low output and part-to-part skew
characteristics make it ideal for workstation, server, and other high
performance clock distribution applications.
CLK_SEL
ICS8534AY-01 REVISION B MARCH 28, 2011
Block Diagram
nPCLK
PCLK
nCLK
CLK
OE
Pullup
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pullup
0
1
Low Skew, 1-to-22 Differential-to-
3.3V LVPECL Fanout Buffer
LE
D
Q
22
22
Q0:Q21
nQ0:nQ21
1
Features
Twenty-two differential LVPECL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
PCLK, nPCLK supports the following input levels: LVPECL, CML,
SSTL
Maximum output frequency: 500MHz
Output skew: 100ps (maximum)
Translates any single-ended input signal (LVCMOS, LVTTL, GTL)
to LVPECL levels with resistor bias on nCLK input
Additive phase jitter, RMS): 0.15ps (typical)
Full 3.3V supply mode
0°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
CLK_SEL
nPCLK
PCLK
nCLK
nQ21
V
V
CLK
Q21
V
CCO
V
CCO
OE
nc
nc
nc
CC
nc
EE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
10mm x 10mm x 1.0mm package body
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-Lead TQFP E-Pad
ICS8534-01
Y package
Top View
©2011 Integrated Device Technology, Inc.
ICS8534-01
DATA SHEET
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
V
V
Q12
nQ12
Q13
nQ13
CCO
CCO

Related parts for 8534BMI-13LF

8534BMI-13LF Summary of contents

Page 1

Low Skew, 1-to-22 Differential-to- 3.3V LVPECL Fanout Buffer General Description The ICS8534- low skew, 1-to-22 Differential-to-3.3V LVPECL Fanout Buffer. The ICS8534-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The ...

Page 2

ICS8534-01 Data Sheet Table 1. Pin Descriptions Number Name 1, 16, 17, 32, V Power CCO 33, 48 Unused 4 V Power CC 5 CLK Input 6 nCLK Input 7 CLK_SEL Input 8 ...

Page 3

ICS8534-01 Data Sheet Table 2. Pin Characteristics Symbol Parameter C Input Capacitance IN R Input Pullup Resistor PULLUP R Input Pulldown Resistor PULLDOWN Function Table Table 3. Control Input Function Table. Inputs OE CLK_SEL Q0:Q21 0 0 LOW 0 1 ...

Page 4

ICS8534-01 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 5

ICS8534-01 Data Sheet Table 4C. Differential DC Characteristics, V Symbol Parameter I Input High Current IH I Input Low Current IL V Peak-to-Peak Voltage; NOTE Common Mode Input Voltage; NOTE 1, 2 CMR NOTE 1: V should ...

Page 6

ICS8534-01 Data Sheet AC Electrical Characteristics Table 3.3V ± 5 CCO Symbol Parameter f Output Frequency OUT t Propagation Delay; NOTE 1 PD tsk(o) Output Skew; NOTE 2, 3 tsk(pp) Part-to-Part Skew; NOTE ...

Page 7

ICS8534-01 Data Sheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase ...

Page 8

ICS8534-01 Data Sheet Parameter Measurement Information 2V±5% V CC, V CCO LVPECL V EE 1.3V± 0.165V - 3.3V LVPECL Output Load AC Test Circuit Par t 1 nQx Qx Par t 2 nQy Qy tsk(pp) Part-to-Part Skew nCLK, nPCLK CLK, ...

Page 9

... PERIOD t odc = t PERIOD - Output Duty Cycle/Pulse Width/Period Applications Information Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. ...

Page 10

ICS8534-01 Data Sheet Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V the bias resistors R1 and R2. The bypass capacitor (C1) ...

Page 11

... CLK/nCLK input driven by the most common driver 1. 50Ω 50Ω LVHSTL R1 IDT 50Ω LVHSTL Driver Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver 3.3V 3.3V R3 125Ω 50Ω 50Ω LVPECL R1 84Ω Figure 3C. CLK/nCLK Input Driven ...

Page 12

ICS8534-01 Data Sheet LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING V input requirements. Figures show interface examples CMR for the PCLK/nPCLK input driven by ...

Page 13

ICS8534-01 Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that ...

Page 14

ICS8534-01 Data Sheet EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the ...

Page 15

ICS8534-01 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS8534-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8534-01 is the sum of the ...

Page 16

ICS8534-01 Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 7. V CCO Q1 Figure 7. LVPECL ...

Page 17

ICS8534-01 Data Sheet Reliability Information θ Table 7. vs. Air Flow Table for a 64 Lead TQFP, E-Pad JA Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS8534-01 is: 1474 ICS8534AY-01 REVISION ...

Page 18

ICS8534-01 Data Sheet Package Outline and Package Dimensions Package Outline - Y Suffix for 64 Lead TQFP, E-Pad Table 8. Package Dimensions for 64 Lead TQFP, E-Pad JEDEC Variation: ACD All Dimensions in Millimeters Symbol Minimum Nominal ...

Page 19

... Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments ...

Page 20

ICS8534-01 Data Sheet Revision History Sheet Rev Table Page T4C ICS8534AY-01 REVISION B MARCH 28, 2011 Description of Change Updated ...

Page 21

... IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT ...

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