MSC8157TVT1000A Freescale Semiconductor, MSC8157TVT1000A Datasheet

MSC8157TVT1000A

Manufacturer Part Number

MSC8157TVT1000A

Description

Digital Signal Processors & Controllers - DSP, DSC Quald8157NE FG1GHz -45 to105c

Manufacturer

Freescale Semiconductor

Datasheet

1.MSC8157TVT1000A.pdf (95 pages)

Specifications of MSC8157TVT1000A

Rohs

yes

Core

SC3850

Data Bus Width

32 bit

Program Memory Size

32 KB

Data Ram Size

512 KB

Number Of Programmable I/os

Number Of Timers

Operating Supply Voltage

0.97 V to 1.05 V

Maximum Operating Temperature

+ 105 C

Package / Case

FCPBGA-783

Mounting Style

SMD/SMT

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Freescale Semiconductor

Data Sheet: Technical Data

MSC8157 Six-Core Digital

Signal Processor

• Six StarCore SC3850 DSP subsystems, each with an

• Chip-level arbitration and switching system (CLASS) that

• 3072 KB 128-bit wide M3 memory, 2048 KBs of which

• 96 KB boot ROM.

• Three input clocks (one global and two differential).

• Six PLLs (three global, two Serial RapidIO, one DDR

• Second generation Multi-Accelerator Platform Engine for

• One DDR controllers with up to a 667 MHz clock (1333

• DMA controller with 32 unidirectional channels

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

SC3850 DSP core, 32 KB L1 instruction cache, 32 KB L1

data cache, unified 512 KB L2 cache configurable as M2

memory in 64 KB increments, memory management unit

(MMU), extended programmable interrupt controller

(EPIC), two general-purpose 32-bit timers, debug and

profiling support, low-power Wait, Stop, and power-down

processing modes, and ECC/EDC support.

provides full fabric non-blocking arbitration between the

cores and other initiators and the M2 memory, shared M3

memory, DDR SRAM controller, device configuration

control and status registers, MAPLE-B, and other targets.

can be turned off to save power.

PLLs).

Baseband (MAPLE-B2) with a second generation

programmable system interface (PSIF2); Turbo encoding

and decoding; Viterbi decoding; FFT/iFFT and DFT/iDFT

processing; downlink chip rate processing; CRC

processing and insertion; equalization processing and

matrix inversion; uplink batch and fast processing. Some

MAPLE-B2 processors can be disabled when not required

to reduce overall power consumption.

MHz data rate), 64/32 bit data bus, supporting up to a total

2 Gbyte in up to four banks (two per controller) and support

for DDR3.

supporting 16 memory-to-memory channels with up to

1024 buffer descriptors per channel, and programmable

priority, buffer, and multiplexing configuration. It is

optimized for DDR SDRAM.

• High-speed serial interface with a 10-lane SerDes PHY that

• QUICC Engine technology subsystem with dual RISC

• I/O Interrupt Concentrator consolidates all chip maskable

• UART that permits full-duplex operation with a bit rate of

• Two general-purpose 32-bit timers for RTOS support per

• Eight programmable hardware semaphores.

• Up to 32 virtual interrupts and a virtual NMI asserted by

• I

• Up to 32 GPIO ports, sixteen of which can be configured as

• Boot interface options include Ethernet, Serial RapidIO

• Supports IEEE Std. 1149.6 JTAG interface

• Low power CMOS design, with low-power standby and

• 45 nm SOI CMOS technology.

supports two Serial RapidIO interfaces, one PCI Express

interface, six CPRI lanes, and two SGMII interfaces

(multiplexed). The Serial RapidIO interfaces support

x1/x2/x4 operation up to 5 Gbaud with an enhanced

messaging unit (eMSG) and two DMA units. The PCI

Express controller supports 32- and 64-bit addressing,

x1/x2/x4 link. The six CPRI controllers can support six

lanes up to 6.144 Gbaud.

processors, 48 KB multi-master RAM, 48 KB instruction

RAM, supporting two communication controllers for two

Gigabit Ethernet interfaces (RGMII or SGMII), to offload

scheduling tasks from the DSP cores, and an SPI.

interrupt and non-maskable interrupt sources and routes

then to INT_OUT/CP_TX_INT, NMI_OUT/CP_RX_INT,

and the cores.

up to 6.25 Mbps.

SC3850 core, four timer modules with four 16-bit fully

programmable timers, two timer modules with four 32-bit

fully programmable timers; and eight software watchdog

timers (SWT).

simple write access.

external interrupts.

interface, I

power-down modes, and optimized power-management

circuitry.

C interface.

C, and SPI.

MSC8157

Document Number: MSC8157

FC-PBGA–783

29 mm x 29 mm

Rev. 1, 12/2012

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