MAX1273EUA+ Maxim Integrated, MAX1273EUA+ Datasheet - Page 12

• Manufacturer Part Number: MAX1273EUA+
• Description: Analog to Digital Converters - ADC FAULT-PROTECTED 12-BIT ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1273EUA+

• Rohs: yes
• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 87 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: uMAX
• Maximum Power Dissipation: 727 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal, External

The MAX1272/MAX1273 use the serial clock to complete
an acquisition. The falling edge of CS does not start a
conversion on the MAX1272/MAX1273. Each conversion
requires a control byte. Programming the fourth bit in the
control byte starts the acquisition sequence. Conversion
starts on the falling edge of the eighth clock cycle after
the start bit.
Keep CS low during successive conversions. If a start bit
is received after CS transitions from high to low, but before
the output bit 4 (D4) becomes available, the current con-
version terminates and a new conversion begins. DOUT
enters high-impedance state when CS transitions high.
SCLK
and controls both acquisition and conversion timing.
Conversion begins immediately after the end of the
acquisition cycle. Successive-approximation bit deci-
sions appear at DOUT on each of the following 12 clock
falling edges (Figure 5). Additional clock falling edges
result in trailing zeros at DOUT.
The maximum running rate of the MAX1272/MAX1273 is
16 clocks per conversion. A clock speed of 1.4MHz
allows for a maximum sampling rate of 87ksps (Figure 6).
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Figure 6. Conversion Timing, 16 Clocks/Conversion
12
DOUT
SCLK
DIN
CS
______________________________________________________________________________________
shifts data in and out of the MAX1272/MAX1273
HI-Z
CONTROL BYTE 0
ACQUISITION
Starting a Conversion
4 SCLKs
MSB
CONVERSION
RESULT 0
12 SCLKs
To achieve the maximum throughput, keep CS low, and
start the control byte after bit 4 (D4) of the conversion in
progress clocks out on DOUT.
If CS is low and SCLK is continuous, guarantee a start
bit by first clocking in 16 zeros.
The MAX1272/MAX1273 power-up in normal operating
mode (all internal circuitry active), and external reference
mode. The MAX1272/MAX1273 require a start bit to initi-
ate a conversion. The contents of the output data register
clear during power-up.
Operate the MAX1272/MAX1273 with an internal or an
external reference. Configure REF as an internal refer-
ence output or an external reference input using the
serial interface. When changing from external reference
mode to internal reference mode, allow 2ms (C
1μF) for the reference to stabilize before taking any
measurement.
The internally trimmed reference provides 4.096V at REF.
Bypass REF to GND with a 1.0μF capacitor (Figure 7a).
CONTROL BYTE 1
LSB
ACQUISITION
4 SCLKs
Applications Information
Internal or External Reference
MSB
CONVERSION
12 SCLKs
RESULT 1
Power-On Reset
Internal Reference
CONTROL BYTE 2
LSB
REF
=