SSTU32866EC/G,557 NXP Semiconductors, SSTU32866EC/G,557 Datasheet - Page 10

• Manufacturer Part Number: SSTU32866EC/G,557
• Description: IC BUFFER 1.8V 25BIT SOT536-1
• Manufacturer: NXP Semiconductors

Specifications of SSTU32866EC/G,557

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935275473557; SSTU32866EC/G; SSTU32866EC/G

Philips Semiconductors
Table 3:
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
[1]
Table 4:
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
[1]
[2]
[3]
[4]
9397 750 14181
Product data sheet
RESET
RESET
Q
H
H
H
H
H
H
H
H
H
H
PPO
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
L
H
H
H
H
H
H
H
H
H
H
H
H
L
0
is the previous state of the associated output.
0
is the previous state of output PPO; QERR
Function table (each flip-flop)
Parity and standby function table
X or floating X or floating X or floating X or floating
X or floating
DCS
DCS
H
H
H
H
H
X
L
L
L
L
7.1 Function table
H
H
H
H
H
H
L
L
L
L
L
L
X or floating
CSR
CSR
X
X
X
X
H
X
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
Inputs
X or floating
L or H
CK
L or H
L or H
L or H
L or H
Inputs
CK
0
Rev. 02 — 11 November 2004
is the previous state of output QERR.
X or floating
L or H
CK
L or H
L or H
L or H
L or H
1.8 V DDR2 configurable registered buffer with parity
CK
= LOW-to-HIGH transition;
= LOW-to-HIGH transition;
(D1 to D25)
X or floating
of inputs = H
Dn, DODTn,
X or floating
DCKEn
even
even
even
even
odd
odd
odd
odd
X
X
H
X
H
X
H
X
H
X
L
L
L
L
X or floating
PAR_IN
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Qn
Q
Q
Q
Q
Q
Q
H
H
H
L
L
L
L
0
0
0
0
0
0
H
H
H
H
X
X
L
L
L
L
= HIGH-to-LOW transition
= HIGH-to-LOW transition
SSTU32866
[2]
Outputs
QCS
PPO
PPO
PPO
Q
Q
Q
Q
H
H
H
H
L
L
L
L
L
0
0
0
0
H
H
H
H
L
L
L
L
L
Outputs
[3]
0
0
[1]
QODT,
QERR
QERR
QCKE
QERR
[1]
Q
Q
Q
Q
10 of 29
H
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
0
0
0
0
0
0