IS42S32400E-7B ISSI, IS42S32400E-7B Datasheet

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IS42S32400E-7B

Manufacturer Part Number
IS42S32400E-7B
Description
DRAM 128M (4Mx32) 143MHz Commercial Temp
Manufacturer
ISSI
Datasheet

Specifications of IS42S32400E-7B

Product Category
DRAM
Factory Pack Quantity
240

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IS42S32400E
IS45S32400E
4M x 32
128Mb SYNCHRONOUS DRAM
FEATURES
• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
• Internal bank for hiding row access/precharge
• Single Power supply: 3.3V + 0.3V
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Auto Refresh (CBR)
• Self Refresh
• 4096 refresh cycles every 16ms (A2 grade) or
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
OPTIONS
• Package:
• Operating Temperature Range:
Integrated Silicon Solution, Inc. - www.issi.com
Rev. E
10/28/10
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-
plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
positive clock edge
– (1, 2, 4, 8, full page)
Sequential/Interleave
64 ms (Commercial, Industrial, A1 grade)
operations capability
command
86-pin TSOP-II
90-ball TF-BGA
Commercial (0
Industrial (-40
Automotive Grade, A1 (-40
Automotive Grade, A2 (-40
o
C to +85
o
C to +70
o
C)
o
C)
o
o
C to +85
C to +105
o
C)
o
C)
KEY TIMING PARAMETERS
ADDRESS TABLE
OVERVIEW
ISSI
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 128Mb SDRAM is organized in 1Meg x 32 bit x 4
Banks.
Parameter
Configuration
Refresh Count
Row Addresses
Column
Addresses
Bank Address
Pins
Autoprecharge
Pins
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
's 128Mb Synchronous DRAM achieves high-speed
Com./Ind.
A1
A2
NOVEMBER 2010
166
100
5.4
6.5
10
-6
6
4M x 32
1M x 32 x 4 banks
4K / 64ms
4K / 64ms
4K / 16ms
A0 – A11
A0 – A7
BA0, BA1
A10/AP
143
100
5.4
6.5
-7
10
7
-75E Unit
133
7.5
5.5
Mhz
Mhz
ns
ns
ns
ns
1

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