IS42S32400E-7B ISSI, IS42S32400E-7B Datasheet - Page 44

• Manufacturer Part Number: IS42S32400E-7B
• Description: DRAM 128M (4Mx32) 143MHz Commercial Temp
• Manufacturer: ISSI

Specifications of IS42S32400E-7B

• Product Category: DRAM
• Factory Pack Quantity: 240

IS42S32400E, IS45S32400E
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the time
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
44
COMMAND
INTERNAL
ADDRESS
CLOCK
INTERNAL
COMMAND
CKE
ADDRESS
CLK
DQ
CLOCK
CKE
CLK
DQ
READ
BANK a,
COL n
T0
NOP
T0
NOP
T1
WRITE
BANK a,
COL n
D
T1
IN
n
NOP
T2
D
OUT
T2
n
of a suspended internal clock edge is ignored; any data
subsequent positive clock edge.
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
T3
D
T3
OUT
n+1
NOP
T4
D
NOP
IN
T4
n+1
Integrated Silicon Solution, Inc. - www.issi.com
NOP
D
T5
OUT
D
DON'T CARE
n+2
NOP
IN
T5
n+2
DON'T CARE
NOP
D
T6
OUT
n+3
10/28/10
Rev. E