SSTV16857CG IDT, Integrated Device Technology Inc, SSTV16857CG Datasheet - Page 2

• Manufacturer Part Number: SSTV16857CG
• Description: IC REGIST BUFF 14BIT DDR 48TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 74SSTVr

Specifications of SSTV16857CG

• Number Of Bits: 14
• Logic Type: Registered Buffer with SSTL_2 Inputs and Outputs
• Supply Voltage: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 14
• Number Of Outputs: 14
• High Level Output Current: -20mA
• Low Level Output Current: 20mA
• Propagation Delay Time: 3.5ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 200(Min)MHz
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IDT™ / ICS™ DDR 14-Bit Registered Buffer
ICSSSTV16857C
DDR 14-Bit Registered Buffer
0002F—10/25/02
General Description
Pin Configuration
The 14-bit ICSSSTV16857C is a universal bus driver designed for 2.3V to 2.7V V
except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge
of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an
LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16857C supports low-power
standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic
“Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always
be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic
“Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable the
differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until the
input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
2
2
3
1
, 4
, 5
, 2
, 4
, 5
P
4
, 3
, 3
N I
2
2
3
2
2
, 9
1
, 6
, 3
, 6
, 3
, 7
, 8
, 8
, 4
4
N
1
, 4
, 5
2
2
4
3
3
3
3
3
3
U
, 2
1
1
, 0
, 9
, 0
, 6
8
9
, 7
4
5
, 1
, 3
M
4
, 2
1
, 7
1
3
4
B
4
4
, 6
2
1
1
, 9
, 0
, 1
6
5
E
, 2
, 0
4
2
R
8
1
3
4
1
, 7
, 8
, 1
, 2
P
R
Q
N I
D
V
V
C
E
G
V
C
D
1 (
1 (
R
L
S
N
D
N
L
D
K
E
: 4
: 4
E
A
K
D
D
Q
#
F
T
) 1
M
) 1
#
E
O
N I
N I
N I
N I
N I
T
U
P
P
P
Y
T
W
W
P
P
P
W
P
P
P
P
U
U
U
U
U
R
R
R
E
U
T
T
T
T
T
T
D
G
D
P
N
C
R
n I
2
O
2
o
e
a
a
e
o
o r
u
p
s
s
a t
a t
g
e r
p t
t u
u
i t i
t e
a
n
t u
o
n i
e v
i t
s
e r
d
e v
a (
u
u
p
s
e f
p t
p
c
t u
i t c
u
p
o l
c
e r
t u
p
y l
o l
e v
p
k c
n
y l
k c
v
c
o l
l o
e
n i
v
n i
w
a t
l o
p
v
l o
p
)
t u
a t
g
t u
a t
e
g
g
e
D
e
DD
E
S
operation and SSTL_2 I/O levels,
C
R
P I
I T
O
N
ICSSSTV16857C
TSD