MAX1157BEUI+ Maxim Integrated, MAX1157BEUI+ Datasheet - Page 8
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MAX1157BEUI+
Manufacturer Part Number
MAX1157BEUI+
Description
Analog to Digital Converters - ADC 14-Bit 135ksps 4.2V Precision ADC
Manufacturer
Maxim Integrated
Datasheet
1.MAX1157AEUI.pdf
(15 pages)
Specifications of MAX1157BEUI+
Rohs
yes
Number Of Channels
1
Architecture
SAR
Conversion Rate
135 KSPs
Resolution
14 bit
Input Type
Single-Ended
Snr
85 dB
Interface Type
Parallel
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Package / Case
TSSOP-28
Maximum Power Dissipation
1026 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
4.096 V
In track mode, the internal hold capacitor acquires the
analog signal (see Figure 4). In hold mode, the T/H
switches open and the capacitive DAC samples the
analog input. During the acquisition, the analog input
(AIN) charges capacitor C
on the second falling edge of CS. At this instant, the
T/H switches open. The retained charge on C
resents a sample of the input. In hold mode, the capac-
itive DAC adjusts during the remainder of the
conversion time to restore node T/H OUT to zero within
the limits of 14-bit resolution. Force CS low to put valid
data on the bus after conversion is complete.
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Figure 2. MAX1157/MAX1159/MAX1175 Timing Diagram
Figure 3. Typical Application Circuit for the MAX1157/MAX1159/
MAX1175
8
_______________________________________________________________________________________
ANALOG
INPUT
0.1µF
+5V ANALOG
R/C
CS
AIN
RESET
AV
DD
MAX1157
MAX1159
MAX1175
AGND DGND
+5V DIGITAL
D0–D13
HOLD
D0–D13
REFADJ
EOC
DV
R/C
CS
EOC
DD
REF
. The acquisition ends
Track and Hold (T/H)
µP DATA
BUS
HIGH-Z
0.1µF
t
t
DH
CSL
0.1µF
14-BIT
WIDE
t
ACQ
t
CSH
HOLD
10µF
DOWN CONTROL
t
DS
REF POWER-
rep-
t
CONV
Select standby mode or shutdown mode with R/C during
the second falling edge of CS (see Selecting Standby or
Shutdown Mode section). The MAX1157/MAX1159/
MAX1175 automatically enter either standby mode (refer-
ence and buffer on), or shutdown (reference and buffer
off) after each conversion depending on the status of
R/C during the second falling edge of CS.
The MAX1157/MAX1159/MAX1175 generate an internal
conversion clock to free the microprocessor from the bur-
den of running the SAR conversion clock. Total conver-
sion time after entering hold mode (second falling edge
of CS) to end-of-conversion (EOC) falling is 4.7µs (max).
CS and R/C control acquisition and conversion in the
MAX1157/MAX1159/MAX1175 (see Figure 2). The first
falling edge of CS powers up the device and puts it in
acquire mode if R/C is low. The convert start CS is
ignored if R/C is high. The MAX1157/MAX1159/
MAX1175 need at least 6ms (C
10µF) for the internal reference to wake up and settle
before starting the conversion if powering up from shut-
down. Reset the MAX1157/MAX1159/MAX1175 by tog-
gling RESET with CS high. The next falling edge of CS
begins acquisition.
The MAX1157/MAX1159/MAX1175 have a selectable
standby or low-power shutdown mode. In standby
mode, the ADC’s internal reference and reference
buffer do not power down between conversions, elimi-
nating the need to wait for the reference to power up
before performing the next conversion. Shutdown mode
t
DV
t
DO
Selecting Standby or Shutdown Mode
DATA VALID
Applications Information
t
t
EOC
BR
HIGH-Z
Starting a Conversion
Power-Down Modes
REFADJ
Internal Clock
= 0.1µF, C
REF
=