ispLSI 1016-80LT44 Lattice, ispLSI 1016-80LT44 Datasheet - Page 14

• Manufacturer Part Number: ispLSI 1016-80LT44
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 1016-80LT44

• Memory Type: EEPROM
• Number Of Macrocells: 64
• Maximum Operating Frequency: 100 MHz
• Delay Time: 20 ns
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 800
• Supply Current: 150 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

1. Pins have dual function capability.
Pin Description
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15 29, 30, 31, 32, 23, 24, 25, 26, 29, 30, 31, 32,
I/O 16 - I/O 19 37, 38, 39, 40, 31, 32, 33, 34, 37, 38, 39, 40,
I/O 20 - I/O 23 41, 42, 43, 44, 35, 36, 37, 38, 41, 42, 43, 44,
I/O 24 - I/O 27 3,
I/O 28 - I/O 31 7,
IN 3
ispEN
SDI/IN 0
MODE/IN 2
SDO/IN 1
SCLK/Y2
Y0
Y1/RESET
GND
V
CC
NAME
1
1
1
1
PIN NUMBERS
15, 16, 17, 18, 9,
19, 20, 21, 22, 13, 14, 15, 16, 19, 20, 21, 22,
25, 26, 27, 28, 19, 20, 21, 22, 25, 26, 27, 28,
2
13
14
36
24
33
11
35
1,
12, 34
PLCC
4,
8,
23
5,
9,
6,
10 1,
PIN NUMBERS
41, 42, 43, 44, 3,
40
7
8
30
18
27
5
29
17, 39
6,
10, 11, 12, 15, 16, 17, 18,
2,
TQFP
28
3,
4
PIN NUMBERS
7,
2
13
14
36
24
33
11
35
1, 23
12, 34
4,
8,
JLCC
13
5,
9,
6,
10
Specifications ispLSI 1016
Input/Output Pins - These are the general purpose I/O
pins used by the logic array.
Dedicated input pins to the device.
Input – Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and
SCLK options become active.
Input – This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as an input pin to load
programming data into the device. SDI/IN 0 also is
used as one of the two control pins for the isp state
machine.
Input – This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as a pin to control the
operation of the isp state machine.
Input/Output – This pin performs two functions. It is a
dedicated input pin when ispEN is logic high. When
ispEN is logic low, it functions as an output pin to read
serial shift register data.
Input – This pin performs two functions. It is a
dedicated clock input when ispEN is logic high. This
clock input is brought into the Clock Distribution
Network, and can optionally be routed to any GLB
and/or I/O cell on the device. When ispEN is logic low,
it functions as a clock pin for the Serial Shift Register.
Dedicated Clock input. This clock input is connected
to one of the clock inputs of all of the GLBs on the
device.
This pin performs two functions:
Ground (GND)
V
CC
– Dedicated clock input. This clock input is brought
– Active Low (0) Reset pin which resets all of the
into the Clock Distribution Network, and can
optionally be routed to any GLB and/or I/O
cell on the device.
GLB and I/O registers in the device.
DESCRIPTION
Table 2 - 0002C-16-isp