ispLSI 2032A-135LTN48 Lattice, ispLSI 2032A-135LTN48 Datasheet - Page 11

• Manufacturer Part Number: ispLSI 2032A-135LTN48
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 2032A-135LTN48

• Rohs: yes
• Memory Type: EEPROM
• Number Of Macrocells: 32
• Maximum Operating Frequency: 167 MHz
• Delay Time: 10 ns
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 1250
• Supply Current: 40 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0
Y0
RESET/Y1
ispEN
SDI/IN 0
MODE
SDO/IN 1
SCLK/Y2
GND
VCC
NC
Pin Description
1
NAME
2
2
2
PIN NUMBERS
15,
19,
25,
29,
37,
41,
3,
7,
2
11
35
13
14
36
24
33
1,
12, 34
44-PIN PLCC
23
16,
20,
26,
30,
38,
42,
4,
8,
17,
21,
27,
31,
39,
43,
5,
9,
18,
22,
28,
32,
40,
44,
6,
10
PIN NUMBERS
40
5
29
7
8
30
18
27
17, 39
6,
9,
13,
19,
23,
31
35,
41,
1,
44-PIN TQFP
28
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
PIN NUMBERS
9,
14,
20,
25,
33,
38,
44,
1,
31
7
32
19
18, 42
6,
12, 24, 36, 48
43
5
8
29
48-PIN TQFP
11
30
10,
15,
21,
26,
34,
39,
45,
2,
11,
16,
22,
27,
35,
40,
46,
3,
Specifications ispLSI 2032/A
13,
17,
23,
28,
37,
41,
47,
4
Global Output Enable input pin.
V
No Connect.
Input/Output Pins — These are the general purpose
I/O pins used by the logic array.
Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
This pin performs two functions:
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and SCLK
controls become active.
Input — When in ISP Mode, controls operation of ISP
state machine.
Output/Input — This pin performs two functions. When
ispEN is logic low, it functions as an output pin to read
serial shift register data. When ispEN is high, it
functions as a dedicated input pin.
Input — This pin performs two functions. When
ispEN is logic low, it functions as a clock pin for the
Serial Shift Register. When ispEN is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
Ground (GND)
Input — This pin performs two functions. When ispEN
is logic low, it functions as an input pin to load
programming data into the device. SDI/IN0 also is used
as one of the two control pins for the isp state machine.
When ispEN is high, it functions as a dedicated input
pin.
CC
DESCRIPTION
Table 2-0002A-08isp/2032