MAX1064ACEG Maxim Integrated, MAX1064ACEG Datasheet - Page 14

• Manufacturer Part Number: MAX1064ACEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1064ACEG

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 400 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 61 dB
• Interface Type: Serial
• Operating Supply Voltage: 2.7 V to 5.5 V, 5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Input (control byte) and output data are multiplexed on a
tri-state parallel interface. This parallel interface (I/O) can
easily be interfaced with standard µPs. Signals CS, WR,
and RD control the write and read operations. CS repre-
sents the chip-select signal, which enables a µP to
address the MAX1060/MAX1064 as an I/O port. When
high, CS disables the CLK, WR, and RD inputs and
forces the interface into a high-impedance (high-Z) state.
Table 2. Control Byte Format
Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
*Channels CH4
Table 4. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
*Channels CH4
14
D7 (MSB)
A2
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
______________________________________________________________________________________
PD1
A1
–
–
0
0
1
1
0
0
1
1
CH7 apply to MAX1060 only.
CH7 apply to MAX1060 only.
A1
0
0
1
1
0
0
1
1
PD0
D6
A0
0
1
0
1
0
1
0
1
A0
0
1
0
1
0
1
0
1
CH0
ACQMOD
+
Digital Interface
D5
CH0
+
-
CH1
+
CH1
SGL/DIF
+
-
D4
CH2
+
CH2
+
-
CH3
The control byte is latched into the device on pins D7–
D0 during a write command. Table 2 shows the control
byte format.
The output format for the MAX1060/MAX1064 is binary in
unipolar mode and two’s complement in bipolar mode.
When reading the output data, CS and RD must be low.
When HBEN = 0, the lower 8 bits are read. With HBEN =
1, the upper 2 bits are available and the output data bits
D7–D2 are set either low in unipolar mode or to the value
of the MSB in bipolar mode (Table 5).
+
UNI/BIP
D3
CH3
+
-
CH4*
+
CH4*
+
-
D2
A2
CH5*
+
CH5*
+
CH6*
-
+
D1
A1
CH6*
CH7*
+
-
Output Format
+
Input Format
D0 (LSB)
A0
CH7*
COM
+
-
-
-
-
-
-
-
-
-