MAX187CEPA Maxim Integrated, MAX187CEPA Datasheet - Page 10

• Manufacturer Part Number: MAX187CEPA
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX187CEPA

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 75 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

When power is first applied, it takes the fully discharged
4.7FF reference bypass capacitor up to 20ms to provide
adequate charge for specified accuracy. With SHDN
not pulled low, the MAX187/MAX189 are now ready to
convert.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiated.
After an internally timed 8.5Fs conversion period, the end
of conversion is signaled by DOUT pulling high. Data can
then be shifted out serially with the external clock.
Power consumption can be reduced significantly by
shutting down the MAX187/MAX189 between conver-
sions. This is shown in Figure 6, a plot of average supply
current vs. conversion rate. Because the MAX189 uses
an external reference voltage (assumed to be present
continuously), it “wakes up” from shutdown more quickly,
and therefore provides lower average supply currents.
The wakeup-time, tWAKE, is the time from SHDN deas-
serted to the time when a conversion may be initiated.
For the MAX187, this time is 2Fs. For the MAX189, this
time depends on the time in shutdown (see Figure 7)
because the external 4.7FF reference bypass capacitor
loses charge slowly during shutdown (see the specifica-
tions for shutdown, REF Input Current = 10FA max).
Figure 6. Average Supply Current vs. Conversion Rate
Maxim Integrated
10,000
1000
100
10
1
Initialization After Power-Up and
0.1
1
CONVERSIONS PER SECOND
10
Using SHDN to Reduce
*REF CONNECTED TO V
MAX187
Starting a Conversion
100
Serial Interface
1k
+5V, Low-Power, 12-Bit Serial ADCs
MAX189*
Supply Current
10k
DD
100k
The actual conversion does not require the external
clock. This frees the FP from the burden of running the
SAR conversion clock, and allows the conversion result
to be read back at the FP’s convenience at any clock rate
from 0 to 5MHz. The clock duty cycle is unrestricted if
each clock phase is at least 100ns. Do not run the clock
while a conversion is in progress.
Conversion-start and data-read operations are controlled
by the CS and SCLK digital inputs. The timing diagrams
of Figures 8 and 9 outline the operation of the serial
interface.
A CS falling edge initiates a conversion sequence: The
T/H stage holds input voltage, the ADC begins to convert,
and DOUT changes from high impedance to logic low.
SCLK must be kept inactive during the conversion. An
internal register stores the data when the conversion is
in progress.
End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing sig-
nal. SCLK shifts the data out of this register any time after
the conversion is complete. DOUT transitions on SCLK’s
falling edge. The next falling clock edge produces the
MSB of the conversion at DOUT, followed by the remain-
ing bits. Since there are 12 data bits and one leading
high bit, at least 13 falling clock edges are needed to
shift out these bits. Extra clock pulses occurring after the
conversion result has been clocked out, and prior to a
rising edge of CS, produce trailing 0s at DOUT and have
no effect on converter operation.
Figure 7. t
WAkE
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0001
vs. Time in Shutdown (MAX187 Only)
MAX187/MAX189
0.001
TIME IN SHUTDOWN (s)
0.01
Timing and Control
0.1
External Clock
1
10
10