MAX187CEPA Maxim Integrated, MAX187CEPA Datasheet - Page 8

• Manufacturer Part Number: MAX187CEPA
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX187CEPA

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 75 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Figure 3a. MAX187 Operational Diagram
Figure 4. Equivalent Input Circuit
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges capaci-
tor C
At this instant, the T/H switches the input side of C
to GND. The retained charge on C
sample of the input, unbalancing the node ZERO at the
comparator’s input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
Maxim Integrated
C
ANALOG INPUT
PACKAGE
GND
AIN
SHUTDOWN
OFF
HOLD
0 TO +5V
INPUT
. Bringing CS low ends the acquisition interval.
ON
REF
C
TRACK INPUT
+5V
4.7µF
SWITCH
HOLD
12-BIT CAPACITIVE DAC
1
2
3
4
C
16pF
-
TRACK
HOLD
0.1µF
V DD
AIN
SHDN
REF
4.7µF
+
MAX187
R
5kI
IN
HOLD
DOUT
ZERO
SCLK
GND
CS
+5V, Low-Power, 12-Bit Serial ADCs
8
7
6
5
HOLD
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
COMPARATOR
represents a
Track/Hold
SERIAL
INTERFACE
HOLD
Figure 3b. MAX189 Operational Diagram
to 0V within the limits of a 12-bit resolution. This action
is equivalent to transferring a charge from C
binary-weighted capacitive DAC, which in turn forms a
digital representation of the analog input signal. At the
conversion’s end, the input side of C
to AIN, and C
The time required for the T/H to acquire an input sig-
nal is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is calcu-
lated by:
where R
input signal, and t
impedances below 5kI do not significantly affect the AC
performance of the ADC.
The ADCs’ input tracking circuitry has a 4.5MHz small-
signal bandwidth, and an 8V/Fs slew rate. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted high-frequency signals into
the frequency band of interest, an anti-alias filter is rec-
ommended. See the MAX274/MAX275 continuous-time
filters data sheet.
ANALOG INPUT
SHUTDOWN
REFERENCE
OFF
0 TO +5V
INPUT
INPUT
IN
ON
= 5kI, R
+5V
0.1µF
HOLD
t
ACQ
MAX187/MAX189
ACQ
charges to the input signal again.
= 9 (R
1
2
3
4
S
0.1µF
V DD
AIN
SHDN
REF
= the source impedance of the
is never less than 1.5Fs. Source
4.7µF
MAX189
S
+ R
DOUT
SCLK
IN
GND
CS
) 16pF
HOLD
8
7
6
5
Input Bandwidth
switches back
HOLD
SERIAL
INTERFACE
to the
8