MAX110BC/D Maxim Integrated, MAX110BC/D Datasheet - Page 17

• Manufacturer Part Number: MAX110BC/D
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX110BC/D

• Number Of Channels: 2
• Architecture: Sigma-Delta
• Conversion Rate: 0.05 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended/Differential
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: +/- 5V
• Maximum Power Dissipation: 842 mW
• Number Of Converters: 1
• Voltage Reference: 5.3 V

* Gain-calibration mode is not available with 102,400 clock cycles/conversion selected.
The data sheet electrical specifications apply to the
device after optional calibration of gain error and offset.
Uncalibrated, the gain error is typically 2%.
Table 3 describes the three steps required to calibrate
the ADC completely.
Once the ADC is calibrated to the selected channel, set
CAL = 0 and NUL = 0 and leave CHS unchanged in the
next control word to perform a signal conversion on the
selected analog input channel.
Calibrate the ADC after the following operations:
Table 5. Clock Divider-Ratio Control
—
—
—
—
—
—
Table 4. Available Conversion Times
Clock duty cycles of 50% ±10% are recommended.
CONV4 CONV3 CONV2 CONV1
when power is first applied
if the reference common-mode voltage changes
after changing conversion speed/resolution.
channel varies significantly. The CMRR of the analog
inputs is 0.25LSB/V.
ages of the two channels are different)
drift with temperature is typically 0.003µV/°C.
if the common-mode voltage of the selected input
after changing channels (if the common-mode volt-
after significant changes in temperature. The offset
1
0
0
0
DV2
0
0
1
1
0
0
1
0
DV4
0
1
0
1
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
______________________________________________________________________________________
0
1
1
0
XCLK or internal RC oscillator connects directly to the ADC; f
XCLK or internal RC oscillator is divided by 4 and connects to the ADC; f
XCLK or internal RC oscillator is divided by 2 and connects to the ADC; f
Not allowed
1
1
0
0
3-Step Calibration
CLOCK CYCLES
CONVERSION
102,400*
10,240
20,480
81,920
PER
RCSEL = GND, DV2 = DV4 = 0, XCLK = 500kHz
NOMINAL CONVERSION TIME
Automatic gain calibration is not allowed in the
102,400 cycles per conversion mode (see
Programming Conversion Time ). In this mode, calibra-
tion can be achieved by connecting the reference volt-
age to one input channel and performing a normal
conversion. Subsequent conversion results can be cor-
rected by software. Do not issue a N N O O - - O O P P command
directly following the gain calibration, as the cali-
bration data will be lost.
The MAX110/MAX111 are specified for 12 bits of accu-
racy and up to ±14 bits of resolution. The ADC’s resolu-
tion depends on the number of clock cycles allowed
during each conversion. Control-register bits 9–12
(CONV1–CONV4) determine the conversion time by
controlling the nominal number of oversampling clock
cycles required for each conversion (OSCC/CONV).
Table 4 lists the available conversion times and result-
ing resolutions.
To program a new conversion time, perform a 3-step
calibration with the appropriate CONV1–CONV4 data
used in Table 3. The ADC is now calibrated at the new
conversion speed/resolution.
DESCRIPTION
163.84
204.80
20.48
40.96
(ms)
OSC
Programming Conversion Time
= f
XCLK
OSC
OSC
.
= f
= f
XCLK
XCLK
4.
2.
CONVERSION
RESOLUTION
12 + POL
13 + POL
14 + POL
14 + POL
(Bits)
17