MAX110BC/D Maxim Integrated, MAX110BC/D Datasheet - Page 19

• Manufacturer Part Number: MAX110BC/D
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX110BC/D

• Number Of Channels: 2
• Architecture: Sigma-Delta
• Conversion Rate: 0.05 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended/Differential
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: +/- 5V
• Maximum Power Dissipation: 842 mW
• Number Of Converters: 1
• Voltage Reference: 5.3 V

Figure 10a. MAX110 Power-Supply Grounding Connections
A 100ms conversion time cannot be achieved with either
10,240 CCPC or 20,480 CCPC modes because f
would be below the minimum 250kHz requirement.
When the gain calibration is performed, the conversion
times change approximately 1% to compensate for the
modulator’s gain error. This slightly degrades the line-
frequency rejection, because the corrected conversion
time is no longer an exact multiple of the line frequency.
Typically, the rejection of 50Hz/60Hz from the converter
is 55dB; i.e., if there is 100mV injection at the reference
or the analog input pin, it will cause an uncertainty of
±0.006%. If the system has large 50Hz/60Hz noise, the
use of internal auto gain calibration is not recommend-
ed. Instead, gain calibration should be done off-chip,
using numerical computation methods.
Table 6. Suggested XCLK Frequencies to Achieve Maximum Rejection of Both 50Hz/60Hz Line
Frequencies
CCPC = Clock Cycles per Conversion
*R = 10
DIVIDER
RATIO
1:1
2:1
4:1
*OPTIONAL
+5V
V
DD
0.8124
1.6248
3.2496
f
(MHz)
XCLK
MAX110 (t
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
4.7 F
0.1 F
81,240 CCPC
______________________________________________________________________________________
MAX110
ACCURACY
RELATIVE
GND
0.025
0.018
0.016
CONVERT
(%)
SUPPLIES
POWER
0.1 F
4.7 F
= 100ms)
V
-5V
SS
(MHz)
f
1.024
2.048
4.096
XCLK
102,400 CCPC
+5V
CIRCUITRY
ACCURACY
DIGITAL
RELATIVE
0.065
0.045
0.030
DGND
GND
(%)
OSC
If you wish to use a configuration other than those sug-
gested in Table 6, you can accomplish similar 50Hz
and 60Hz line-frequency rejection off-chip by averag-
ing several conversions.
For minimal noise, bypass each supply to GND with a
0.1µF capacitor. A ground plane should also be placed
under the analog circuitry. To minimize the coupling
effects of stray capacitance, keep digital lines as far
from analog components and lines as possible. Figure
10 shows the suggested power-supply and ground-
plane connections.
Figure 10b. MAX111 Power-Supply Grounding Connections
__________Applications Information
DIVIDER
*R = 10
RATIO
1:1
2:1
4:1
*OPTIONAL
+5V
V
DD
0.4062
0.8124
1.6248
(MHz)
f
XCLK
MAX111 (t
81,240 CCPC
4.7 F
0.1 F
Layout, Grounding, Bypassing
MAX111
ACCURACY
RELATIVE
GND
0.030
0.025
0.022
CONVERT
(%)
SUPPLIES
POWER
= 200ms)
AGND
GND
f
(MHz)
0.512
1.024
2.048
XCLK
102,400 CCPC
+5V
CIRCUITRY
ACCURACY
RELATIVE
DIGITAL
0.030
0.025
0.023
DGND
(%)
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