S9S12GN32F0MFT Freescale Semiconductor, S9S12GN32F0MFT Datasheet - Page 539
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S9S12GN32F0MFT
Manufacturer Part Number
S9S12GN32F0MFT
Description
16-bit Microcontrollers - MCU 16-bit32k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12GN16F0CFT.pdf
(1292 pages)
Specifications of S9S12GN32F0MFT
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
32 KB
Data Ram Size
2048 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
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15.3.2.12 ATD Conversion Result Registers (ATDDRn)
The A/D conversion results are stored in 16 result registers. Results are always in unsigned data
representation. Left and right justification is selected using the DJM control bit in ATDCTL3.
If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must
be written with the compare values in left or right justified format depending on the actual value of the
DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be
stored there at the end of the conversion but is lost.
Attention, n is the conversion number, NOT the channel number!
Read: Anytime
Write: Anytime
15.3.2.12.1 Left Justified Result Data (DJM=0)
Table 15-21
result registers for left justified data. Compare is always done using all 12 bits of both the conversion result
and the compare value in ATDDRn.
Freescale Semiconductor
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11
0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15
Reset
W
R
15
0
shows how depending on the A/D resolution the conversion result is transferred to the ATD
= Unimplemented or Reserved
For conversions not using automatic compare, results are stored in the result
registers after each conversion. In this case avoid writing to ATDDRn except
for initial values, because an A/D result might be overwritten.
14
0
Figure 15-14. Left justified ATD conversion result register (ATDDRn)
13
0
resolution
10-bit data
8-bit data
Table 15-21. Conversion result mapping to ATDDRn
A/D
12
0
MC9S12G Family Reference Manual, Rev.1.23
11
0
0
0
DJM
Result-Bit[11:0]
10
0
Result-Bit[11:4] = conversion result,
Result-Bit[3:0]=0000
Result-Bit[11:2] = conversion result,
Result-Bit[1:0]=00
conversion result mapping to
0
9
NOTE
0
8
0
7
0
6
Analog-to-Digital Converter (ADC10B16CV2)
ATDDRn
0
5
4
0
0
0
3
0
0
2
0
0
1
0
0
0
541
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