S9S12GA192F0MLHR Freescale Semiconductor, S9S12GA192F0MLHR Datasheet - Page 511
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S9S12GA192F0MLHR
Manufacturer Part Number
S9S12GA192F0MLHR
Description
16-bit Microcontrollers - MCU 16BIT192KFLASH 11264 RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GA192F0MLHR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
192 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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14.3.2.8
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0008
CMPE[11:0]
CC[3:0]
Reset
Field
Field
11–0
3–0
W
R
15
0
0
Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1,
CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO
mode (FIFO=0) the conversion counter is initialized to zero at the beginning and end of the conversion sequence.
If in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counter wraps around when its
maximum value is reached.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.
Compare Enable for Conversion Number n (n= 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion
number, NOT channel number!) — These bits enable automatic compare of conversion results individually for
conversions of a sequence. The sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT
register.
For each conversion number with CMPE[n]=1 do the following:
CCF[n] in ATDSTAT2 register will flag individual success of any comparison.
0 No automatic compare
1 Automatic compare of results for conversion n of a sequence is enabled.
ATD Compare Enable Register (ATDCMPE)
= Unimplemented or Reserved
1) Write compare value to ATDDRn result register
2) Write compare operator with CMPHT[n] in ATDCPMHT register
14
0
0
13
0
0
Figure 14-10. ATD Compare Enable Register (ATDCMPE)
Table 14-16. ATDSTAT0 Field Descriptions (continued)
0
0
Table 14-17. ATDCMPE Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
11
0
10
0
0
9
0
8
Description
Description
0
7
CMPE[11:0]
0
6
Analog-to-Digital Converter (ADC12B12CV2)
0
5
4
0
0
3
0
2
0
1
0
0
513
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