S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 887
S9S12G48F0MLH
Manufacturer Part Number
S9S12G48F0MLH
Description
16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G48F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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26.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
Freescale Semiconductor
Address
Offset Module Base + 0x0000
Reset
& Name
0x000D
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
FRSV2
FRSV3
FRSV4
FRSV5
FRSV6
FRSV7
FOPT
W
R
FDIVLD
Flash Clock Divider Register (FCLKDIV)
0
7
W
W
W
W
W
W
W
R
R
R
R
R
R
R
NV7
7
0
0
0
0
0
0
FDIVLCK
Figure 26-4. FTMRG48K1 Register Summary (continued)
= Unimplemented or Reserved
0
6
Figure 26-5. Flash Clock Divider Register (FCLKDIV)
NV6
= Unimplemented or Reserved
MC9S12G Family Reference Manual, Rev.1.23
6
0
0
0
0
0
0
0
5
NV5
5
0
0
0
0
0
0
0
4
NV4
4
0
0
0
0
0
0
0
3
NV3
FDIV[5:0]
3
0
0
0
0
0
0
48 KByte Flash Module (S12FTMRG48K1V1)
0
2
NV2
2
0
0
0
0
0
0
NV1
0
1
1
0
0
0
0
0
0
NV0
0
0
0
0
0
0
0
0
0
889
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