74F382PC Fairchild Semiconductor, 74F382PC Datasheet - Page 2

• Manufacturer Part Number: 74F382PC
• Description: IC ARITHMETIC LOGIC 4BIT 20-DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F382PC

• Logic Type: Arithmetic Logic Unit
• Supply Voltage: 4.5 V ~ 5.5 V
• Number Of Bits: 4
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74F382

www.fairchildsemi.com
Unit Loading/Fan Out
Functional Description
Signals applied to the Select inputs S
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit performs the arith-
metic functions for either active HIGH or active LOW oper-
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the C
Ripple expansion is illustrated in Figure 2. The overflow
output OVR is the Exclusive-OR of C
HIGH signal on OVR indicates overflow in twos comple-
ment operation. Typical delays for Figure 2 are given in
Figure 1.
n
A
C
C
C
C
Total Delay
input of the least significant package.
1
n
n
n
n
A
B
S
C
C
OVR
F
or B
to F
to C
to C
to C
0
0
0
0
n
n
–F
Pin Names
–A
–B
–S
1
n
n
n
4
3
3
3
2
to C
Path Segment
4
4
4
, OVR
n
4
FIGURE 2. 16-Bit Ripply Carry ALU Expansion
0
n
–S
A Operand Inputs
B Operand Inputs
Function Select Inputs
Carry Input
Carry Output
Overflow Output
Function Outputs
3
2
FIGURE 1. 16-Bit Delay Tabulation
and C
determine the
Description
n
4
; a
2
Toward
27.2 ns
6.5 ns
6.3 ns
6.3 ns
8.1 ns
Function Select Table
H
L
—
F
LOW Voltage Level
HIGH Voltage Level
HIGH/LOW
50/33.3
50/33.3
50/33.3
1.0/4.0
1.0/4.0
1.0/1.0
1.0/5.0
S
U.L.
H
H
H
H
L
L
L
L
0
Select
S
H
H
H
H
L
L
L
L
C
Output I
20 A/ 2.4 mA
20 A/ 2.4 mA
20 A/ 0.6 mA
20 A/ 3.0 mA
1
n
Input I
1 mA/20 mA
1 mA/20 mA
1 mA/20 mA
Output
27.1 ns
6.5 ns
6.3 ns
6.3 ns
8.0 ns
4
—
, OVR
IH
OH
S
H
H
H
H
/I
L
L
L
L
/I
2
IL
OL
Clear
B Minus A
A Minus B
A Plus B
A
A
AB
Preset
Operation
B
B