FXLA102L8X Fairchild Semiconductor, FXLA102L8X Datasheet - Page 12

• Manufacturer Part Number: FXLA102L8X
• Description: TRANSLATOR DUAL 2BIT 8-MICROPAK
• Manufacturer: Fairchild Semiconductor

Specifications of FXLA102L8X

• Logic Function: Translator, Bidirectional, 3-State
• Number Of Bits: 2
• Input Type: Voltage
• Output Type: Voltage
• Data Rate: 140Mbps
• Number Of Channels: 1
• Number Of Outputs/channel: 2
• Differential - Input:output: No/No
• Propagation Delay (max): 3.5ns
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MicroPak™
• Supply Voltage: 1.1 V ~ 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FXLA102L8XTR

© 2009 Fairchild Semiconductor Corporation
FLXA102 • Rev. 1.0.2
I/O Architecture Benefit
The FXLA102 I/O architecture benefits the end user,
beyond level translation, in the following three ways:
Auto Direction without an external direction pin.
Drive Capacitive Loads. Automatically shifts to a
higher current drive mode only during “Dynamic Mode”
or HL / LH transitions.
Lower Power Consumption. Automatically shifts to
low-power mode during “Static Mode” (no transitions),
lowering power consumption.
The FXLA102 does not require a direction pin. Instead,
the I/O architecture detects input transitions on both side
and
corresponding output. For example, for a given channel,
if both A and B side are at a static LOW, the direction
has been established as A  B, and a LH transition
occurs on the B port; the FXLA102 internal I/O
architecture automatically changes direction from A  B
to B  A.
During HL / LH transitions, or “Dynamic Mode,” a strong
output driver drives the output channel in parallel with a
weak output driver. After a typical delay of approximately
10ns – 50ns, the strong driver is turned off, leaving the
weak driver enabled for holding the logic state of the
channel. This weak driver is called the “bus hold.” “Static
Mode” is when only the bus hold drives the channel. The
automatically
transfers
the
data
to
the
12
bus hold can be over ridden in the event of a direction
change. The strong driver allows the FXLA102 to quickly
charge and discharge capacitive transmission lines
during dynamic mode. Static mode conserves power,
where I
Bus Hold Minimum Drive Current
Specifies the minimum amount of current the bus hold
driver can source/sink. The bus hold minimum drive
current (II
DC Electrical tables. The intent is to maintain a valid
output state in a static mode, but that can be overridden
when an input data transition occurs.
Bus Hold Input Overdrive Drive Current
Specifies the minimum amount of current required (by
an external device) to overdrive the bus hold in the
event of a direction change. The bus hold overdrive
(II
Electrical tables.
Dynamic Output Current
The strength of the output driver during LH / HL
transitions is referenced on page 8, Dynamic Output
Electrical Characteristics, I
ODH
, II
CC
ODL
HOLD
is typically < 5µA.
) is V
) is V
CC
dependent and guaranteed in the DC
CC
dependent and guaranteed in the
OHD
, and I
OLD
.
www.fairchildsemi.com